In this experiment, your knowledge to analyze a sequential circuit which is explained in section 3.4 of the course book will be tested.
Let there be an input X, a 2-bit output Y1Y0 and a sequential circuit connecting these two as shown below.
- Initially, all state register values are zero (S2 =0,S1 =0,S0 =0).
- The reset should be synchronous to the falling edge of the clock.
Note: Components given above are inverter, and, or, nor, xor, xnor and state register, respectively.
0.1.3 Preliminary Work
Before the experiment, you should prepare the following materials:
- State the inputs and outputs of the state registers.
- State the inputs and outputs of the combinational block of the sequential circuit.
- Write each output (including next state bits) as a function of the inputs.
- Draw the truth table for the combinational circuit (Hint: use the functions in theprevious step).
- Draw the finite state machine by using the table obtained in previous step.
- How many unreachable states does the finite state machine contain? (No explanation, only short answer)
- Briefly explain the relation between the input and the output. (Hint: which patterns in the input results in different outputs)
- Write the behavioral level verilog code for the corresponding finite state machine.
- Write the verilog code for the testbench waveform in order to test different inputcombinations. (keep the initial state as State 0, i.e. S2S1S0 =000)