Aim

In this experiment, your knowledge to minimize the number of gates by using decoder and multiplexer gate.

# 0.1.2 Problem

A circuit takes five inputs denoted as *x*_{4}*,x*_{3}*,x*_{2}*,x*_{1}, and *x*_{0}. This circuit has only one output *y*. The output is determined as shown in the following table.

x_{4} |
x_{3} |
y |

0 | 0 | PRIME?(x_{2},x_{1},x_{0}) |

0 | 1 | EVEN?(x_{2},x_{1},x_{0}) |

1 | 0 | MAJ?(x_{2},x_{1},x_{0}) |

1 | 1 | EQ?(x_{2},x_{1},x_{0}) |

We define PRIME, EVEN, MAJ, and EQ as follows. *x*_{2}*x*_{1}*x*_{0 }represents a three bit unsigned number.

*PRIME*?(*x ,x *_{,x }_{) = }1 *x*2*x*1*x*0 is prime

otherwise

*EV EN*?(*x ,x *_{,x }_{) = }1 *x*2*x*1*x*0 is even

otherwise

Most of *x*_{2}*,x*_{1}*,x*_{0 }are 1 otherwise

1 *x*_{2 }= *x*_{1 }= *x*_{0 }otherwise

You are only allowed to use one 2×4 Decoder, one 8×1 Multiplexer, at most 2

binary logic gates (AND, OR, XOR, XNOR, NAND, NOR) and infinite number of NOT gates to complete the design of this circuit.

# 0.1.3 Preliminary Work

Before the experiment, you should prepare following materials:

- Fill the truth table.
- Draw the circuit of your design.
- Write a verilog code for the circuit drawn in the previous step. Verilog codeshould have two components. First, you have to write behavioural level verilog code which implements the functionality of multiplexer and/or decoder. Then, you have to write the gate level verilog code (source.v) for your circuitry which uses the implemented components and additional built-in gates (i.e.
*AND*,*OR*,*NAND*,*NOR*,*XOR*, or*XNOR*).

2

- Write the verilog code for the testbench (testbench.v) in order to test all possibleinput combinations.

Then, submit the your code, and your report under the name *<*StudentID1*> <*StudentID2*> *PRE2.zip through Moodle

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