Objective: To implement RTL Design (structural datapath and behavioral controller) of Greatest Common Denominator (GCD) of two numbers to be tested on a FPGA board.
Description: Design a GCD for two 4-bit numbers. It will output the binary value of the greatest common divisor of those two numbers. The numbers will be input via the dip switches, the result will be output via the LEDs, and control is done via push buttons.
- Input X uses switches SW7-SW0.
- Input Y uses switches DIP9-4 to DIP8-1.
- Input START uses the pushbutton BTN0. This button needs to be debounced.
- Input RESET uses the pushbutton BTN3.
- Output GCD OUT uses LEDs LD7-LD0.
- Output DONE uses the LED LD9.
The data path components must be constructed structurally. You can create individual behavioral components (Adder, Comparator, Register, etc.) for each element in the data path. Registers are the only clocked component, and they should be triggered by the clock on the opposite edge than that of the Controller FSM. All non-register components must be purely combinational. Registers should have an enable signal for control, and a separate reset signal.
- Write structural Verilog for data path and behavioral Verilog for controller (FSM). Use the design we discussed in the class. The FSM Verilog code should strictly follow the FSM template.
- Synthesize the design and verify its functionality on the FPGA.
Submit a zipped archive consisting of: (a) A concise report that includes your Verilog code and simulation results; (b) Verilog Models and Test bench. Include a README file.
Report Organization (A template is provided on Canvas):
- Cover sheet
- Problem 1: Your design details, Verilog Code, Test Bench, and Simulation Results (Waveforms)
- Problem 2: Pin mapping file and Synthesis report.
- Feedback: Hours spent, Exercise difficulty (Easy, Medium, Hard)