Objective: To learn and practice advanced sequential hardware design in Verilog and synthesizable Verilog based circuit implementation on FPGA board.
| Port | Width | I/O | Function |
| max_count | 7 | I | Set the maximum counter value |
| run | 1 | I | Set run mode;0 = set, 1=run |
| digit_2 | 4 | O | Ten digit BCD output |
| digit_1 | 4 | O | Ones Digit BCD output |
Figure 1: Counter Top-Level Block Diagram
Table 2
| Port | Width | I/O | Component | Mapping |
| Run | 1 | I | Dip Switches | SW7 |
| Max_count | 7 | I | Dip Switches | SW6 (MSB) SW0 (LSB) |
| Clk | 1 | I | Dip Switches | USER_CLK |
| Digit_1 | 4 | O | GPIO LEDS | LED3 (MSB) LED0 (LSB) |
| Digit_2 | 4 | O | GPIO LEDS | LED7 (MSB) LED4 (LSB) |
Description:
Design a programmable counter that outputs BCD and has a range of 0-99. The counter must count from zero to a user-input value. The valid input range is 0-99; if a higher number is input, the counter must not output beyond 99 (decimal). The output from your design should be in binary-coded decimal. You will need to design a binary counter that counts at least to 99dec, and a module which converts the binary output to two-digit BCD. A single-bit input, called run, determines the operation of the counter. When run is 0, the counter is set to zero and does not count. The user can set the maximum value here, using an input called max_count. When run is set to 1, the counter starts counting from zero, and stops when it reaches the maximum. Any changes to max_count is ignored when run is set to 1. Your design will have two 4-bit outputs; digit 1 and digit 2. Each is used to output one BCD digit. Digit 2 is the tens digit, digit 1 is the ones digit.
- Create a Verilog design (See Figure 1) which will provide the required functionality.
- Exhaustively test the design to ensure that it works under all conditions.
- Use 100 MHz to synthesize and map the design on ANVYL board using table 2.
Deliverables: (1) A concise PDF report that includes your Verilog code and simulation results; (2) A zipped file of your design files (Verilog Models and test benches.) Include a README file. Organize your files in folders named Problem1, Problem2.
Report Organization (A template is provided on Canvas):
- Cover sheet
- Problem 1 and 2: Verilog Code, Test Bench, and Simulation Results (Waveforms)
- Problem 3: Pin Mapping file
- Feedback: Hours spent, Exercise difficulty (Easy, Medium, Hard)
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