The aim in this experiment is to find the expression with the lowest cost for combinational logic circuits and implement them. In this experiment, you are allowed to use ‘&’ (Bitwise AND), ‘|’ (Bitwise OR), ‘∼’ (Bitwise NOT), and ‘{}’ (Concatenate) operations. Other operations such as ‘+’, ‘-’, ‘*’, ‘/’, ‘*<<*’, ‘*>>*, ‘ˆ’, always, switch case, and if else are forbidden.

# 2 Preliminary

- For the function
*F*_{1 }given in Equation 1, apply the following operations:- Find its prime implicants using Karnaugh diagram.
- Find its prime implicants using Quine-McCluskey method.
- Create prime implicant chart and find the expression with the minimum cost with 2 units of cost for each variable and 1 unit of cost for complement of a variable.
- Design and draw the lowest cost expression using NOT, AND, and OR gates.
- Design and draw the lowest cost expression using only NAND gates.
- Design and draw the lowest cost expression using a single 8:1 Multiplexer and NOT gates.

*F*_{1}(*a,b,c,d*) = ∪_{1}(0*,*1*,*3*,*5*,*8*,*10*,*13*,*14) + ∪* _{φ}*(2

*,*7

*,*11

*,*12) (1)

- Design and draw the functions
*F*_{2 }and*F*_{3 }given in Equations 2 and 3 using ONE single 3:8 decoder, 2-input OR gates (*x*^{0 }represents the complement of*x*).

F_{2}(a,b,c) = abc^{0 }+ a^{0}c |
(2) |

F_{3}(a,b,c) = ab^{0}c^{0 }+ bc |
(3) |

1

*Experiment 2: Combinational Logic Circuits*

3 Experiment

# Part 1

Please implement the circuit that you have designed in Preliminary 1.d. section using NOT, AND, and OR modules in Verilog. You should write these “gates” as modules and use them later in your implementations. In other words, for example, when you need to apply an AND operation to two input wires, you should use the modules you have written before, rather than using operators like “&” or “|” directly. Following the implementation, please run simulations for various input combinations to validate your design.

# Part 2

Please implement the circuit that you have designed in Preliminary 1.e. section using only NAND modules in Verilog. You should implement the gate as a module and use it later in your implementations. Following the implementation, please run simulations for various input combinations to validate your design.

# Part 3

Please implement the circuit that you have designed in Preliminary 1.f. section using a

8:1 multiplexer and NOT gates in Verilog. You should write the multiplexer and NOT gate as modules and use them later in your implementations. Following the implementation, please run simulations for various input combinations to validate your design.

# Part 4

Please implement the circuit that you have designed in Preliminary 2 section using a 3:8 decoder and OR gates in Verilog. You should write the decoder and OR gate as modules and use them later in your implementations. Following the implementation, please run simulations for various input combinations to validate your design.

# 4 Report

You should show your work of Preliminary study on the report in detail. You can use any tool for creating tables (for Preliminary 1.a., 1.b. and 1.c.) and circuit designs (for Preliminary 1.d., 1.e. and 1.f.). You may attach them to the report as figures by properly referencing them in the text.

Your report should also contain information about the results of your simulations. If your implementations are not fully correct, discuss what the source of the errors might

2

be in your report.

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