[SOLVED] VHDL Circuit Design and Simulation SQL

VHDL Circuit Design and Simulation

VHDL Modelling and Simulation of a Polynomial Evaluator

a. Assignment Aims

This assignment will enable you to become familiarised with, and gain experience of the industrially relevant software, Intel Quartus Prime (digital system design) and ModelSim (simulation software). The design and modelling of digital circuitry will be undertaken using a hardware description language (HDL) called VHDL within the Quartus Prime software. VHDL is an industry standard programming language for representing complex digital circuits, at different levels of abstraction, quickly and easily.  The VHDL  code will be compiled and simulated using the ModelSim software, to enable the functionality of the design to be verified.

An introductory tutorial for the software tools, on how to implement VHDL code and verify the function/operation through simulation, is provided.

b. Learning Outcomes:

The following learning outcomes will be assessed by this assessment

Knowledge and Understanding Outcomes

Apply modern digital CAD tools and Hardware Description Languages (HDLs) to the development and analysis digital design problems.

Evaluate the methodologies, techniques, performance limitation factors and cost drivers for the design of digital systems.

Ability Outcomes

Demonstrate an awareness of developing technologies related to integrated circuit design.

Analyse data for a design problem (before solving) using an appropriate design methodology and assess the quality of the solution.

c. Assignment Brief Section 1

The VDHL code provided in  Figure  1,  models a digital circuit that  evaluates a polynomial function for a fixed ‘x’ parameter value and 4 variable inputs (a0  to a3), using a high-level of abstraction. The polynomial being evaluated is;

f(x) = a0 + a1x + a2x2 + a3x3

Note:

The input ai enter in series with a3 first followed by a2 etc, (a3, a2, a1, a0)

Value of x is fixed.

a, x and fx are all integers.

The value of fx will be updated every clock cycle.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

use ieee.std_logic_arith.all;

ENTITY Section1_NHE2483 IS

PORT (    clk, res : IN  BIT;

ai, x      : IN  INTEGER:=0;

fx         : OUT INTEGER:=0);

END Section1_NHE2483;

ARCHITECTURE bhv OF Section1_NHE2483 IS

SIGNAL reg1 : INTEGER:=0;

BEGIN

PROCESS

BEGIN

WAIT UNTIL (clk’EVENT AND clk = ‘1’);

IF res = ‘1’ THEN reg1 <= 0;

ELSE reg1 <= x * (ai + reg1);

END IF;

END PROCESS;

fx <= reg1 + ai;

END bhv;

Figure 1 High-Level VHDL Code – Polynomial Evaluator

NOTE: The code in Figure 1 can be copied directly into the Intel Quartus Prime software

Tasks

o Compile the VHDL code, given in Figure 1, in the Intel Quartus Prime software – guidance document on how to use the Quartus software is provided.

o Simulate the code using an appropriate input test sequence of values for x and ai.

Documentary evidence required,

o Generate a block diagram, for the code, showing the Entity section – input and output signals.

o Annotate  the given VHDL code, detailing  the  operation  of  each section of the code. Use flow/block diagram to aid explanation of Architecture section.

o Annotate  the output  waveforms, with a clear explanation of the reasons for the selection of the test value and compare to theoretical calculations.

o Note: Annotation is the process of adding text to make it easy for the reader to see how and if the circuit is functioning and how it relates to the theory.

Section 2

Tasks

o Redevelop the VHDL code, given in section 1, for the polynomial evaluator at a lower level of abstraction, where the inputs, outputs and internals signals are represented as vectors (std_logic_vector) instead of Integer values – integers don’t relate directly to hardware, whereas vectors do.

o Input values,

ai

•    range from 0 – 7 (000 to 111: 3 bits)

•   enter in series with a3 first (a3, a2, a1, a0)

x

•    range from 0 – 3 (00 to 11: 2 bits).

o Determine and appropriate range, in terms of bits for output f(x).

•   Documentary evidence required,

o VHDL code – annotated detailing the operation of each section of the code.

o Output waveforms, with clear annotation detailing the reasons for the selection of the test vectors and a comparison to theoretical calculations.

Section 3

Refining section 2 VHDL code.

•    Tasks

o Part A

Since only one value in four (clock pulses), at output f(x) is correct, modify the code so that only the valid outputs are seen at the output.

o Part B

Adapt the code so that any size of the polynomial or input vectors can be modified using the GENERIC term.

•    Polynomial  functions  –  limit  the  possible  function  size  to  the following,

f(x) = a0 + a1x + a2x2

f(x) = a0 + a1x + a2x2 + a3x3

f(x) = a0 + a1x + a2x2 + a3x3 + a4x4

o Generic parameters required – 3,4 or 5.

a and x – vector size – limit to values 2 to 4 bits wide.

o Generic parameters required 2,3 or 4.

fx vector size – note: adapting the respective vector and function sizes will also impact on the size of the fx vector.  In order to simplify the code, calculate the maximum possible vector size for fx and fix to that vector size (no need to make this vector size Generic).

Documentary evidence required,

o VHDL code – annotated detailing the operation of each new section of the code.

o Output waveforms, with clear annotation detailing the reasons for the selection of the test vectors and a comparison to theoretical calculations.

Note:

You may discuss design ideas with other students but detailed copying of VHDL code, annotation and simulations is forbidden and will be penalised in accordance with the University’s regulations on Academic Misconduct.

Marking Scheme

Criterion	Weighting %
1. VHDL Code and System Design:	Total 70
• Section 1 – Explanation of VHDL code operation	15
• Section 2 – VHDL code design and operation	25
• Section 3 Part A – VHDL code design and operation	15
• Section 3 Part B – VHDL code design and operation	15
2. Verification and Annotation of Simulations:	Total 30
• Section 1 Detail the input vectors, annotated simulations with comparison to theory.	10
• Section 2 Detail the input vectors, annotated simulations with comparison to theory.	10
• Section 3 Parts A-B : Detail the input vectors, annotated simulations with comparison to theory. Note – only simulation required with details of progress relative to Parts A-B.	10