ELEC0028 Advanced Digital Design Coursework Assignment

Introduction

The aim of this assignment is to write a SystemVerilog description of a RISC-V microprocessor, and simulate its operation using Icarus Verilog.

Download and install Icarus Verilog, GTKWave and Visual Studio Code on your laptop computer, following the instructions in the document ‘Icarus Verilog and GTKWave Installation and User Guide’ on the ELEC0028 Moodle page. (Note: If you used these apps last year on the ELEC0010 course, they may still be working on your computer, and do not need to be reinstalled.)

The deliverable is a report (a pdf file, to be uploaded using the coursework submission tab on the Moodle page). The report should include:

• the SystemVerilog code you have written,

• the simulation results in text form and/or graphical form,

  Inst Name Type Syntax Opcode funct3 funct7 Description

• comments on whether the design functions as expected.

add sub or and slt	ADD SUB OR AND Set Less Than	R R R R R	add rd, rs1, rs2 sub rd, rs1, rs2 or rd, rs1, rs2 and rd, rs1, rs2 slt rd, rs1, rs2	0110011 0110011 0110011 0110011 0110011	0x0 0x0 0x6 0x7 0x2	0x00 0x20 0x00 0x00 0x00	rd = rs1 + rs2 rd = rs1  rs2 rd = rs1  rs2 rd = rs1 & rs2 rd = (rs1 < rs2) ? 1:0
addi ori andi	ADD Immediate OR Immediate AND Immediate	I I I	addi rd, rs1, imm ori rd, rs1, imm andi rd, rs1, imm	0010011 0010011 0010011	0x0 0x6 0x7		rd = rs1 + imm rd = rs1  imm rd = rs1 & imm
lw sw	Load Word Store Word	I S	lw rd, imm(rs1) sw rs2, imm(rs1)	0000011 0100011	0x2 0x2		rd = M[rs1+imm][31:0] M[rs1+imm][31:0] = rs2[31:0]
beq jal jalr	Branch == Jump and Link Jump and Link Reg	B J I	beq rs1, rs2, imm jal rd, imm jalr rd, rs1, imm	1100011 1101111 1100111	0x0 0x0		If (rs1 == rs2) PC = PC+imm rd = PC+4; PC = PC+imm rd = PC+4; PC = rs1+imm
lui	Load Upper Imm	U	lui rd, imm	0110111			rd = imm << 12

Figure 1 shows the microarchitecture of the processor, which can execute all of the instructions in Table 1. Figure 2 shows the internal circuit design of the microprocessor’s Arithmetic Logic Unit (ALU), and the table of ImmSrc control signal values.

PCSrc1:0

ResultSrc1:0

MemWrite ontrol ALUControl2 Unit ALUSrc

ImmSrc2:0 RegWrite

CLK

WE3

1

RD1

2 RD2

3 Register

D3 File

Extend

Im

6:0

14:12 C 0

31:25

ELEC0028 Advanced Digital Design – Coursework

ALUResult

00 PCNext

01

CLK

PC

A

Instr

RD

19:15

A

24:20

SrcA

ALU

Zero

CLK

A RD ReadData 00

2

10

Reset

Instruction Memory

11:7 A A

W

0 SrcB

1

Data 01

Memory 10

and IO

WD

31:7

+ PCPlus4

4

mExt

PCTarget

+

Figure 1 RISC-V microarchitecture

CPUOut CPUIn

Result

N

Cout

N

N

N

N

[N-1]

N

N

N

N

32

32

+

[31] Sum

32

100 110011

32

011

32 32 32

010 001 000

3

ALUControl

ALUControl0

0

1

ZeroExt

A B

Instruction type	ImmSrc2:0
R	000
I	000
S	001
B	010
J	011
U	100

N

Result

32

Result Zero

Figure 2 Top: RISC-V Arithmetic Logic Unit (ALU). Bottom: Table of ImmSrc values

00 PCNext P

01

10

5 WE3

A1

RD1

0

A2 RD2

A3 Register

WD3 File

P

R

M

Control A

Unit

A

I

R

ALU

B

A RD

Data

Memory and IO

WD

A

RD

Instruction

Memory

3

6:0

14:12

31:25

CSrc1:0

esultSrc1:0

emWrite LUControl2:0 LUSrc mmSrc2:0 egWrite

ALUResult

CLK

CLK

4

1

CLK

2

Instr

19:1

6

SrcA

7

C

Zero

24:2

11:7

ReadData 00

01

10

Reset

0 Src

1

5

PCTarget

+

CPUOut CPUIn

31:7

s4

mmExt

You should create a hierarchical design, with the sub-blocks which are highlighted in Figure 3 implemented as individual SystemVerilog modules. These will then be instantiated by the top- level module, which will have the module name risc_v.

+ PCPlu

4

Extend

I

Result

The sub-blocks in Figure 3 are listed in Table 2.

Table 2 RISC-V sub-blocks

Sub-block number in Figure 3	Sub-block function	SystemVerilog module name
1	Program Counter	program_counter
2	Instruction Memory	instruction_memory
3	Control Unit	control_unit
4	Register File	reg_file
5	Extend	extend
6	Arithmetic Logic Unit	alu
7	Data Memory and Input/Output	data_memory_and_io

List of tasks

Task 1

• Copy out and complete Table 3, specifying the control signals for each of the instructions.

Table 3 Table of RISC-V control signals, to copy out and complete

Inst	RegWrite	ImmSrc2:0	ALUSrc	ALUControl2:0	MemWrite	ResultSrc1:0	PCSrc1:0
add	1	000	0	000	0	00	00
sub
or
and
slt
addi
ori
andi
lw
sw

beq

jal jalr lui

[10 marks]

Task 2

The set of SystemVerilog modules can be found in the folder ‘RISC-V SystemVerilog modules’ on the ELEC0028 Moodle page. Some of the modules are already complete (instruction_memory, reg_file, and data_memory_and_io). The other modules are incomplete. The machine code program is stored in hexadecimal form in a text file (program.txt), which should be saved in the same folder as the SystemVerilog files. An example machine code program is included in the ‘RISC-V SystemVerilog modules’ folder on the Moodle page.

• Study the SystemVerilog code of the completed modules, and note the following:

  • The machine code program is written into the array prog in the instruction_memory module using using the $readmemh system task.

  • The Instruction Memory and Data Memory are both byte-addressable.

  • The input and output of the processor are memory-mapped:

    • Load word (lw) from data memory address 0xFFFFFFFC causes the input to the microprocessor (CPUIn) to be written into the destination register.

    • Store word (sw) to data memory address 0xFFFFFFFC causes the value in the source register to be output from the microprocessor (CPUOut).

      the microprocessor to start executing the stored program from memory address 0.

  • The entire 32-bit instruction (Instr[31:0]) is input to the extend module. Use the appropriate subset of these bits to generate the extended immediate (ImmExt) output from the extend module.

  • In the alu module, describe the ALU’s functionality using a case statement within a combinational cyclic behaviour (always_comb). Addition and subtraction can be described with the SystemVerilog syntax:

sum = a + b; sum = a – b;

respectively. The simulator (and circuits produced by synthesis tools) will automatically use 2’scomplement numbers to represent negative values, and to carry out subtraction.

[25 marks]

Task 3

• Choose a set of test inputs to test each of the modules you have written.

• Write testbenches to test the individual modules, with the testbench names program_counter_tb, control_unit_tb, extend_tb and alu_tb.

• Carry out simulations to test these modules using Icarus Verilog. Present the results in text form and/or graphical form (timing diagrams using GTKWave). Comment on whether each module functions as expected.

  [20 marks]

  Task 4

• Complete the top-level module (risc_v.sv), interconnecting the individual modules to form the microarchitecture in Figure 3.

  • Multiplexers can be described in the top-level module using if..else statements,

    case statement, or conditional statements, e.g.:

    assign mux_out = (select) ? a : b;

  • The adder circuit generating PCTarget can be written using the syntax

• Read through the machine code program in the file ‘program.txt’ provided in the folder in Moodle, and disassemble the program (i.e., write out the program as RISC-V assembly code). Write a description of what you would expect the program to do.

• Compile the complete RISC-V microprocessor design and run the simulation, using Icarus Verilog. Present the results in text form and/or graphical form (timing diagrams using GTKWave). Comment on whether the microprocessor functions as expected.

  [25 marks]

  Task 5

• Write a RISC-V assembly program which tests each of the assembly instructions in Table 1. Assemble the program (i.e., convert your assembly program to machine code, expressed in hexadecimal), and save the code in the text file ‘program.txt’.

• Compile the complete RISC-V microprocessor design, including your new program, using Icarus Verilog. Carry out the simulation. Present the results in text form and/or graphical form (timing diagrams using GTKWave). Comment on whether the microprocessor functions as expected.

[20 marks]

End of assignment