In Lab 2, we are going to implement an ALU (Arithmetic Logic Unit) and a shifter by Verilog. Through this lab, students will learn how to design the function unit of a processor to support its instruction set. Note that you should design these circuits in gate- level as combinational logic instead of sequential logic. The ALU and shifter designed in this lab may also be used in most of the succeeding lab units.

2. Lab Description

A. Attached files

The attached file is composed of ALU.v, ALU_1bit.v, Full_adder.v, Shifter.v, and TestBench.v. Please use these files to accomplish the design of your ALU and shifter. You may create additional module (.v file) for your design, if necessary.

B. Arithmetic Logic Unit (ALU)

The block diagram of the 32-bit ALU for this lab is shown in Figure 1, and the operations and corresponded control signals for this ALU are described in Table 1.

Table 1: Control signals and the output of ALU

Figure 1: 32-bit ALU

Besides computing to result, generate two output signals described as follows:

• zero: A 1-bit output control signal. Itis set to 1 when the computing result of ALU,

result, is 0; else, is clear to 0.

• overflow: A 1-bit output control signal. It is set to 1 when the computing result of ALU is overflow; else, is clear to 0.

Note that all operations in Table1 are 32-bit operations. Therefore, in this lab, you should implement a typical 1-bit ALU first and then build the 32-bit ALU by 32 1-bit ALUs.

1. 1-bit ALU

The logic diagram of a typical 1-bit ALU to be implemented in this lab is shown in Figure 2.

Figure 2: 1-bit ALU

1. 32-bit ALU

The block diagram of the 32-bit ALU to be implemented is shown in Figure 3.

Figure3: Connection between 32 1-bit ALU As shown in Figure 3, each input signal of ALU.v will be connected to the corresponding input of 1-bit ALU. Moreover, carryOut of ALU_i will be connected to carryIn of ALUi+1

The design of ALU31 is different from that of other typical 1-bit ALUs. There are two additional signals generated by ALU31 and are described as follows:

• set: A 1-bit control line, is generated by ALU31 and send to ALU0.
• overflow: A 1-bit output control signal, is set to 1 when overflow occurs.

C. Shifter

The block diagram of the shifter to be implemented in this lab is shown in Figure 4, and the basic operations and the corresponded control signals of the shifter t are described in Table 2.

Figure 4: Shifter

Table 2: Control signals and the output of shifter

This shifter is 32bits, which may logical left/right shift by X bits position each time.

Please implement it as a combinational circuit.

Shifter.v contains the following inputs and outputs:

• sftSrc: A 32-bit input data, is the source data of the shifter
• leftRight: A 1-bit input control signal. When it is set to 1, the shifter perform logical left shift; else, does logical right shift.
• shamt: A 5-bit input data, represents the number of bit positions to be shifted
• result: A 32-bit output data, which represents the shifting result of the shifter.

3. Environment

Follow the steps in attached ppt to install iverilog.

You can use TestBench.v and the test data to test your code.

Put all .v files and .txt(test and ans file) in the same path and use iverilog to compile TestBench.v.

If you create additional .v file, you need to include it in TestBench.v.