CS359: Computer Architecture
Memory Hierarchy Design
(Computer Architecture: Appendix B and Chapter 2)
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Department of Computer Science and Engineering
Memory Hierarchy Design
p2.1 Cache Organization
pVirtual Memory
pSix Basic Cache Optimizations
pTen Advanced Optimizations of Cache Performance
pMemory Technology and Optimizations
pVirtual Memory and Protection
pProtection: Virtual Memory and Virtual Machines
Memory Hierarchy Design
Computer Memory
p Memory is a large linear array of bytes. m Each byte has a unique address
(location).
m Byte of data at address 0x100, and 0x101
p Most computers support byte (8-bit) addressing.
p Data may have to be aligned on word (4 bytes) or double word (8 bytes) boundary.
m int is 4 bytes
m double precision floating point is 8 bytes
p 32-bit vs. 64-bit addresses!
m we will assume 32-bit for rest of course, unless otherwise stated!
Memory Hierarchy Design
Our Naïve View of Memory
What issues do we need to worry about in implementing the memory system?
Memory Hierarchy Design
Performance Gap between Memory and Processor
Memory Hierarchy Design
A Typical Memory Hierarchy
Take advantage of the principle of locality to present the user with (1) as much memory as is available in the cheapest technology, (2) but at the speed offered by the fastest technology
Secondary Memory (Disk)
On-Chip Components
Second Level Cache (SRAM)
Access time (ns): 0.1 1 10 100 Size (bytes): 100 10K M G
Cost: highest
Main Memory (DRAM)
Instr Data Cache Cache
ITLB DTLB RegFile
Memory Hierarchy Design
SRAM and DRAM
p Caches use SRAM for speed and technology compatibility
m Fast (typical access times of 0.5 to 2.5 nsec)
m Low density (6 transistor cells), higher power, expensive ($2000 to $5000 per GB in 2008)
m Static: content will last “forever” (as long as power is left on)
q Main memory uses DRAM for size (density)
● Slower (typical access times of 50 to 70 nsec)
● High density (1 transistor cells), lower power, cheaper ($20 to $75 per GB in 2008)
● Dynamic: needs to be “refreshed” regularly (~ every 8 ms)
– consumes1% to 2% of the active cycles of the DRAM
● Addresses divided into 2 halves (row and column)
– RAS or Row Access Strobe triggering the row decoder
– CAS or Column Access Strobe triggering the column selector
SRAM: 6 transistors
DRAM: 1 transistor
Memory Hierarchy Design
Principle of Locality:
Programs tend to reuse data and instructions near those they have used recently, or those were recently referenced themselves.
Temporal locality
• Recently referenced items are likely to be referenced in the near future.
Spatial locality
• Items with nearby addresses tend to be referenced close together in time.
Memory Hierarchy Design
The Memory Hierarchy: How Does it Work?
p Temporal Locality (locality in time)
mIf a memory location is referenced then it will tend
to be referenced again soon
Þ Keep most recently accessed data items closer to the processor
p Spatial Locality (locality in space)
mIf a memory location is referenced, the locations with nearby addresses will tend to be referenced soon
Þ Move blocks consisting of contiguous words closer to the processor
Memory Hierarchy Design
Control Datapath
Devices Input
Secondary Memory (Disk)
Main Memory
Memory Hierarchy Design
Real Organization of Hierarchy
Memory Hierarchy Design
Characteristics of the Memory
4-8 bytes (word) L1$
8-32 bytes (block) L2$
1 to 4 blocks
Increasing distance from the processor in access time
Main Memory Secondary Memory
(the relative) size of memory at each level
Inclusive–
what is in L1$
is a subset of
what is in L2$
is a subset of
what is in MM
subset of is in
SM 1,024+ bytes (disk sector = page)
Memory Hierarchy Design
Memory Hierarchy Design
Terminology
p Block (or line): the minimum unit of information that is present (or not) in a cache
p Hit Rate: the fraction of memory accesses found in a level of the memory hierarchy
m Hit Time: Time to access that level which consists of (1) Time to access the block + (2) Time to determine hit/miss
p Miss Rate: the fraction of memory accesses not found in a level of the memory hierarchy Þ 1 – (Hit Rate)
m Miss Penalty: Time to replace a block in that level with the corresponding block from a lower level which consists of
(1) Time to access the block in the lower level + (2) Time to transmit that block to the level that experienced the miss + (3) Time to insert the block in that level + (4) Time to pass the block to the requestor
Hit Time << Miss PenaltyMemory Hierarchy Design How is the Hierarchy Managed?pregisters « memory mby compilerpmain memory « disksmby the operating system (virtual memory)mphysical address mapping assisted by the hardware (TLB)pcache « main memorymby the cache controller hardware程序代写 CS代考加微信: assignmentchef QQ: 1823890830 Email: [email protected]
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