Do not minimize. The grader has only the plain answers.
- Write two VHDL statements that implement the truth table below Just use and or and not with parenthesis. the answer starts x <=
y <=
a b c | x y
+-
0 0 0 | 0 0
0 0 1 | 1 1
0 1 0 | 0 0
0 1 1 | 0 1
1 0 0 | 1 0
1 0 1 | 0 1
1 1 0 | 1 0
1 1 1 | 0 0
Use this style, do not minimize.
- Write the VHDL statement that implements the logic diagram
+-
a |OR |____
b | | |
+-+ | +-
|NAND|
+-+ | |
c |NOR |_____| |__
d | | | | |
+-+ | | |
| | |
+-+ | | | |
e |NOT || +-+ | +-
+-+ || OR |
| | g
f | |
+-
Be sure to include the semicolon in VHDL statements,
else you lose one point for each that is missing.
- Draw the logic diagram that represents the VHDL statement
g <= ((not a and b) xor (c or not d or e)) or (f and not e);
- For the following schematic, Ripple Carry wiring:
Use a, b, e and f all as four ones. e.g. a <= 1111 etc.
4a) what is the six bit result s.
4b) given that the time from any input to any output in the
full adder is 2T, how much time does the longest path from
any input to any output require? the answer is ____ T
- For the following schematic, Carry Save wiring:
Use a, b, e and f all as four ones. e.g. a <= 1111 etc.
5a) what is the six bit result s.
5b) given that the time from any input to any output in the
full adder is 2T, how much time does the longest path from
any input to any output require? the answer is ____ T
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