[SOLVED] EEE8088 Reconfigurable Hardware Design Audio Processing on DE1

EEE8088

Reconfigurable

Hardware Design

Audio Processing on DE1

Aims and Objectives

Aim: an approach to the solution

Objectives:

● Specification and Architecture

● Reading the manual: codec specs and protocols

● I2C Interface, discussion of the template

● DSP Interface, discussion of the template

● Simulation with ModelSim

● If labs accessible: Debugging with SignalTap, signal generator and oscilloscope

Design Specifications

● Source-destination: analogue audio codec

● Input/Output: analogue audio converted into 16- bit, 44.1kHz digital stream.

● Read the CODEC manual and choose the configuration modes (several valid options available)

● Processing: FIR filter on FPGA, 8 taps

● Language: VHDL

WM8731 Datasheet rev. 4.8 is used for reference

Terasic DE1-SoC development board, Cyclone V FPGA

Design Architecture

Start with the CODEC!

CODEC Configuration

● Analogue I/O – Line

● Gain 1 unit, or 0dB

● Audio CD sampling format; Left channel

● Read “Normal Mode Sample Rates” and see Table 1, mode 01000 (or 11000)

● No CODEC filters, no bypass, no any fancy things…

CODEC Clock/Reset

● Clock is denoted as MCLK or AUD_XCK, see p.41, “Normal Mode Sample Rates”

● Power-on reset circuit is built-in

● Software reset by writing to register 0000000, see Table 30, p. 50, “Register Map Description”

CODEC Interfaces

● Control Interface: 2-wire MPU, a.k.a. I2C

– Used for the initial configuration

– Any speed up to 500kHz (choose 100kHz)

● Digital Audio Interface: 3-wire DSP, a.k.a. I2S

– Input and output digital audio streams

– Master mode (configured on init via I2C)

– DSP mode (configured on init via I2C)

– Speed 64×44.1 kHz

I2C Bus Format

● Bus clock of “almost” arbitrary frequency

● 3 bytes of information – 24 bits total

● Start transition

● Stop transition

● 3 Ack bits – high impedance state

Control Information

● 24 bits (see previous slide), MSB first

– 7 bits device address, fixed 0011010

– 1 bit R/W bit – 0 for writing

– 7 bits register address, see Table 30

– 9 bits of register data, see Table 30

● The Digital Audio Interface will not work without the configuration supplied via Control Interface!