[SOLVED] ECE 511 Analog Integrated Circuits Homework 7 Fall 2024

ECE 511: Analog Integrated Circuits

Homework #7

Fall 2024

Due:  Wed, Nov. 6, 2024

For the OTA below, assume that IT  = IM=40 µA,  |Vt |=0.4 V, Vdd=3V, all transistors are designed for |Veff |=0.15V, and  λ=0.2 V-1.  Assume M13-M14 are 1/10 the size of M11-M12.  Likewise, assume M15- M16 are 1/11 the size of M3-M4.  Neglect body effect and VLIN.

(For all calculations, using a spreadsheet could be helpful, as you could use it later in project work.)

1.    Which input is positive and which input is negative?

2.    What are the values needed for RN  and RP  to result in wide-swing cascode biasing with Vsafe=50mV?  (see lecture 11 for the definition of Vsafe)

3.    On a schematic, annotate all known voltages and currents.

4.    Create a table of all the small-signal parameters of all transistors, using following format:

5.    What is the differential-mode gain of this OTA in dB?

6.    What is the CMRR of this OTA in dB?  (refer to lecture 8, current-mirror load, being careful to take the proper output impedance in common mode)

7.    What is the peak-to-peak output swing?

8.    What is the common-mode input range, in terms of max and min values?

9.    What is the maximum peak-to-peak swing of a signal that could be provided to this OTA if it were placed in unity-gain feedback and we wanted the loop gain to remain maximum?

10. What is the total dc power consumption of this circuit?

11. What value of CC  is needed to be added at the output to set the gain-bandwidth product to 250MHz?  (careful of the 2*PI factor)

12. What is the slew rate (in V/µs) of this OTA when using this value of CC?  Slew rate is defined in lecture 21 as follows:  , where Icap  is defined as the maximum or minimum current that can flow into or out of the capacitor. The SR indicates how fast the output voltage can change and is one key speed metric for the circuit.