[Solved] ECE 4250/7250-Lab2-Design Simulation Using Modelism II

ECE 4250/7250VHDL AND PROGRAMMABLE LOGIC DEVICESLAB#2DESIGN SIMULATION USING MODELSIM III. ObjectiveThis objective of this lab is to use ModelSim to create and simulate a 6-bit fullsubtractor.II. ProblemsIn this lab you have to design and create a 6-bit full subtractor by using 6 fullsubtractors as the component. Your design should have two 6-bit inputs (A, B), a borrowininput (Bin), a 6-bit subtract output (C) and a borrow-out output (Bout) as shown infigure 1

III. Instructions1. Create a new project in ModelSim. Then, develop and simulate your design inthe program. Finally, display your results in the wave window of the program at least 3samples.2. Add or change time delay of your full subtractor. Show the simulation, describethe difference from the pervious simulations and explain the reason.3. Draw a completed block diagram of your design showing both internal andexternal signals.