[Solved] DigitalCircuit Homework 2- ASM Chart-VHDL

Given the following ASM chart

Write a complete VHDL code to implement the architecture using 3 processes. (Use a positive edge clk and a low level asynchronous Reset)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; Entity Parallel_To_Serial is

port( CLK, RESET, WR: in std_logic;

Data : in std_logic_vector(6 downto 0)

TXD : out std_logic);

End Parallel_To_Serial;

architecture BEHAVIOR of Parallel_To_Serial is

You have to submit two files:

1. A VHDL code to implement your ASM.
2. A testbench file to simulate and test your design. You should cover the following cases:

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