Hello and welcome to Project 2! In this project, youll start by implementing some basic sequential logic elements. Then, youll build three missing pieces of the LC-3 hardware which were removed as well as writing the microcode for the bulk of LC-3 instructions.

Please read through the entire document before starting. Often times things are elaborated on below where they are introduced, so reading the entire document can give you a better grasp on things. Start early and if you get stuck, theres always Piazza or office hours.

1.1 Latches

The first thing youll implement are sequential logic elements. These allow us to retain data in a circuit, in other words remember a previous value. This allows us to have logic that depends on the last event that happened in a sequence of events, in other words sequential logic.

The goal of this section is to produce a register. A register is an edge-triggered sequential logic circuit element that can store a binary value. For more on this section, see Implementation: Latches

1.2 The LC-3

The LC-3 datapath weve discussed in class contains a lot of pieces very similar to circuits weve seen or even made before (e.g. an ALU, a register file with 8 edge-triggered general purpose registers, a RAM unit, etc.). One piece weve mostly referred to as a black-box in the past is the Micro-controller. Its responsible for controlling the entire datapath, and getting it to properly execute the instructions that we give it. Thats a big task! So how does the Micro-controller actually work? In this project, well build a few datapath components to develop some familiarity with the LC-3, and then well actually write the microcode which allows the Micro-controller to function.

The micro-controller, shown above, is a finite state machine. It has 59 possible states (holy cow!), and because it is implemented in the binary reduced style, it needs 6 bits to store all its possible states. It also has 49 output bits of output flags, including 10 which are used to determine the next state and 39 which extend throughout the datapath to control other pieces of the LC-3. That would be a lot of very complex hardwareif it were built entirely in hardware.

It turns out there is an easier way. We can actually use a ROM (Read-only Memory) in order to specify the behavior of each distinct state in the state machine (e.g. each instruction will map to a series of entries in the ROM. Each entry in the ROM represents something called a micro-state, which is an individual state of the finite state machine and a potentially a component of a slightly larger sequence of states known as a macro-state. FETCH is a macro-state, and each of the execute stages of LC-3 instructions is also a macro-state. Each of the macro-states will require between 1-5 micro-states to complete, depending on the complexity of the instruction.

What does a ROM entry look like? We encourage you to go ahead and open up microcode.xlsx, on the microcode sheet, to follow along.

A ROM entry is basically a long binary string. The last few bits of it cover the transition to the next stateyou dont need to worry about this at all during this project, so weve covered it in dark grey on the right. Do NOT modify the NEXT bits, or stuff will break. Each of the other bits corresponds to a signal asserted onto the datapath during that clock cycle. For this project, we only require that you implement 19 of the signals asserted onto the datapath (notice that three of these are 2-bit signals).

Weve also simplified and removed a number of micro-states which arent directly a part of the LC-3s main instructions. There are only 36 micro-states in this project. Weve also given you the microcode for some of these micro-states. Your task is to fill in the rest and finish the LC-3 micro-controller!

1.3 LC3 Files Provided

• sim a large CircuitSim file containing the LC-3 AND a Manual LC-3 which does not need to be modified in any way but is simply present as a tool for you while writing microcode. You should only modify the CC-logic, PC, and ALU subcircuits in this file.
• xlsx an Excel document in which you will write your microcode. Do not touch cells that have been blacked out
• dat a text file which you can paste your microcode into and then import into the LC-3.
• tests/ a subdirectory which contains a number of test cases you can use to verify the functionality of your circuit and microcode.
• proj2-tester-1.0.jar a local tester you can use to verify the functionality of your CC-logic, PC, and ALU subcircuits. This tester is also available on Gradescope (where it will be a part of your grade).
• LC-3InstructionsDetail.pdf a PDF with descriptions and pseudocode for each instruction.

1.4 Elements to complete

1. Implement the ALU, PC, and CC-Logic subcircuits in sim.
2. Complete the lc-3 microcode in xlsx, in the microcode sheet.

2 Implementation

2.1 Latches

For this part of the assignment you will build your own register from the ground up. For more information about each subcircuit refer to your textbook.

2.1.1 RS Latch

You will start by building a RS latch using NAND gates, as described in your textbook. RS Latch is the basic circuit for sequential logic. It stores one bit of information, and it has 3 important states:

1. R=1 S=1 : This is called the Quiescent State. In this state the latch is storing a value, and nothing is trying to change that value.
2. R=1 S=0 : By changing momentarily from the Quiescent State to this state, the value of the latch ischanged so that it now stores a 1.
3. R=0 S=1 : By changing momentarily from the Quiescent State to this state, the value of the latch ischanged so that it now stores a 0.

Once you set the bit you wish to store, change back to the Quiescent State to keep that value stored. Notice that the circuit has two output pins; one is the bit the latch is currently storing, and the other is the opposite of that bit.

Note: In order for the RS Latch to work properly, you must not set both R and S to 0 at the same time.

• Build your circuit in the RS Latch subcircuit in the latches.sim file

2.1.2 Gated D Latch

Using your RS latch subcircuit, implement a Gated D Latch as described on the textbook. The Gated D Latch is made up of an RS Latch as well as two additional gates that serve as a control. With that addition not only can we control what value is stored by the latch, but also when that value will be saved. The value of the output can only be changed when Write Enable is set to 1. Notice that the Gated D Latch subcircuit only has one output pin, so you should disregard the inverse output of your RS Latch.

• Implement this circuit in the Gated D Latch subcircuit in the latches.sim file
• You are not allowed to use the built-in SR Flip-Flop in CircuitSim to build this circuit

2.1.3 D Flip-Flop

Using the Gated D Latch circuit you built, create a D Flip-Flop. A D Flip-Flop is composed of two Gated D Latches back to back, and it implements edge triggered logic. Your D Flip-Flop output should be able to change on the rising edge, which means that the state of the D Flip-Flop should only be able to change at the exact instant the clock goes from 0 to 1.

• Implement this circuit in the D Flip-Flop subcircuit in the latches.sim file.

2.1.4 Register

Using the D Flip-Flop you just created, build a 4-bit Register. Your register should also use edge-triggered logic. The value of the register should change on the rising edge.

• This circuit will be implemented in the Register subcircuit in the latches.sim file

2.2 Completing the LC3 SubCircuits

Note: DO NOT move the position of the inputs and outputs in the LC3 subcircuits; this could break the rest of the LC3 simulator.

2.2.1 ALU

You will need to build the ALU (Arithmetic Logic Unit) subcircuit in LC3.sim.

The ALU will perform one of 4 functions and Output it depending on the ALUK signal:

1. ALUK = 0b00: A + B
2. ALUK = 0b01: A & B
3. ALUK = 0b10: NOT A
4. ALUK = 0b11: PASS A

You should be able to use what you learned from HW3 to populate this subcircuit easily.

2.2.2 PC

You will need to build the PC (Program Counter) subcircuit in LC3.sim.

The PC is a 16 bit register that holds the address of the next instruction to be executed. During the FETCH stage, the contents of the PC are loaded into the memory address register (MAR), and the PC is updated with the address of the next instruction. There are three scenarios for updating the PC:

1. The contents of the PC are incremented by 1. Selected when PCMUX = 0b00.
2. The result of the ADDR (an address-adding unit) is the address of the next instruction. The outputfrom the ADDR should be stored in the PC. This occurs if we use the branching instruction, (BR). Selected when PCMUX = 0b01.
3. The value on the BUS is the address of the next instruction. The value on the BUS should be storedinto the PC. An example of this functionality is the JMP instruction.

Selected when PCMUX = 0b10.

The PC should only be loaded on a rising clock edge when the LD.PC signal is on.

Ensure that you dont reach the unused case (PCMUX = 0b11) of the circuit, or else spooky stuff might happen (undefined behavior in LC-3).

2.2.3 CC-Logic

The LC-3 has three condition codes: N (negative), Z (zero), and P (positive). These codes are saved on the next rising edge after the LC-3 executes Operate or Load instructions that include loading a result into a general purpose register, such as ADD and LDR.

For example, if ADD R2, R0, R1 results in a positive number, then NZP = 001.

The LC-3 appendix on canvas should help determine which instructions set the Condition Code.(See page 5 pf PattPatelAppA.pdf)

The CC subcircuit should set N to 1 if the input is negative, set Z to 1 if the input is zero, and set P to 1 if the input is positive. Only 1 bit in NZP should be set at any given time. Zero is not considered a positive number.

Bit 2 (the MSB) is N, Bit 1 is Z, Bit 0 is P.

With that in mind, set the correct bit and implement this circuit in the CC-Logic subcircuit.

Implement this circuit in the subcircuit CC-Logic.

Hint: you can use a comparator for this subcircuit! They are found in the Arithmetic tab in CircuitSim.

2.2.4 Checking Your Work

Once complete, run the autograder

java -jar proj2-tester-1.0.jar

inside the Docker container in the command prompt in the same directory as your LC3.sim file.

If all of the relevant tests pass, youve completed this part of the project. Congrats!

2.3 Using Manual LC-3 (for testing only)

• Once you have your PC, CC-Logic, and ALU complete you can begin working on the meat of this project, understanding how LC-3 works.
• In lecture and lab we have covered the signals in the datapath and how they are used when tracing an instruction.
• The first thing you will want to do is use the Custom-Bus, GateBUS, and LD.IR signals to set a custom IR value on the next rising edge. Until you figure out the states for fetch, you can use these steps to set your IR with any instruction you want to work on.
• Once you have an idea of how fetch works, you can load some instruction(s) in the RAM. In order to do that:
  1. right-click the RAM near the bottom of the Manual LC-3 circuit
  2. select edit contents
  3. click Load from file
  4. locate and select one of the provided test files in the project (ex: addand.dat)
  5. close the edit contents menu
• Now that you have loaded the RAM with a program, you can fetch instructions into the IR.
• Now that you have an instruction in the IR, you can start executing it. In order to do that you can turn on the different signal pins on the right in order to control the datapath and move data around like we did in lecture/lab. Once you think you know how an instruction is executed, you can enter it into the microcode spreadsheet, the process for which is outlined below.
  • Tests inside the tests/ directory have a comment at the end of the .asm file which explains the system state after the end of the programs execution. You must ensure that this is the system state after you have run every instruction sequentially through the simulator.
  • To test whether the program acted correctly, go to the LC-3 circuit and double-click into the REG FILE element that is placed in the datapath. Note: you should not just click into the REG FILE subcircuit, as this will not properly load the state of the specific REG FILE element thats built into the LC-3, just some generic REG FILE.
  • Bonus tip: Use Ctrl-R to reset the simulator state and easily clear RAM and registers to 0 in order to test again.
• If you are familiar with LC-3 assembly (you will learn it over the course of the next two weeks), you are welcome to write your own test programs to verify your code. Make sure that your programs do not start at x3000, as in this project only we will start execution at x0000 for simplicitys sake. You can compile LC-3 assembly projects to machine code by following the LC-3 ISA, and then create your own RAM.dat files. We cant guarantee that well be able to help with these test cases in office hours, though.

2.4 Writing the Microcode

Note: For this section, DO NOT MODIFY the DRMUX or SR1MUX signals, or the bits labelled

NEX in the microcode.xlsx excel sheet (these signals are all greyed out).

• Now that youve developed some familiarity with the datapath and gotten a chance to act as the micro-controller and run the execute stage of instructions on the Manual LC-3, you can complete the final part of the project: writing the microcode for a number of micro-instructions on the LC-3!
• In xlsx Excel document, microcode sheet, there exist a number of macro-states. Among them are FETCH and the execute stages for most instructions supported by the LC-3 (weve removed several macro-states related to trap and interrupt handling). For each macro-state, weve provided space for the micro-states which will make up that macro-state, and for each micro-state, weve handled all of the logic related to transitioning to the next micro-state. Weve also implemented a small subset of the macro-states in order to provide inspiration to you, our students (youre welcome).
• You should complete all the remaining macro-states by filling in their micro-states.

If you notice that the output column to the right of the blacked-out columns (column AH) is showing artifacts like #NAME?, try opening the Excel spreadsheet in your Georgia Tech Office 365 Online Excel workspace. Sign in to Office 365 with Georgia Tech credentials, select Excel, and then choose Upload and open to edit the excel sheet online.

2.4.1 How to Test your Micro-code

At any time that you want to test your micro-code, you can export it from the .xlsx file and apply it to LC-3 hardware by following these steps. IMPORTANT NOTE: Passing all of the tests provided does not guarantee that you have a functional datapath, any number of coincidences could cause you to get the correct output with incorrect functionality. As always, we reserve the right to grade with additional test cases.

1. At the bottom of the xlsx file select the output tab.
2. Copy all of column D from row 1 through row 64
3. Paste the result into ROM.dat
4. Ensure that ROM.dat is in the same directory as ./cs2110docker.sh (or some subdirectory)
5. In Docker CircuitSim, open LC3.sim. Navigate to the Fsm subcircuit. This circuit contains themicro-controller.
6. Right-click on the ROM and select Edit contents.
7. Select Load from file
8. navigate to and select ROM.dat. This will load the ROM.
9. Navigate to the LC-3 subcircuit.
10. You can now load a program into the RAM, following the instructions above in the Manual LC-3 sections.
11. To run the LC-3, you can manually click through the CLK signal or use Ctrl-K to start or stop theautomatic clock. After your program has stopped executing (you can tell when its finished running because it will HALT and the datapath will stop changing).
12. Tests inside the tests/ directory have a comment at the end of the .asm file which explains the system state after the end of the programs execution. To test whether the program acted correctly, go to the LC-3 circuit and double-click into the REG FILE element that is placed in the datapath. Note: you should not just click into the REG FILE subcircuit, as this will not properly load the state of the specific REG FILE element thats built into the LC-3, just some generic REG FILE.

2.4.2 Tips, Tricks, Resources

This is all pretty crazy to take in at first. But its not the end of the world if you make sure to use the resources available to you. Here are some options:

• LC-3 Datapath Diagram: Canvas Files Resources LC-3DatapathDiagram.pdf
• LC-3 ISA Quick Sheet: Canvas Files Resources LC-3ISA.pdf
• LC-3 Instructions Detail Sheet: LC-3InstructionsDetail.pdf, in this project.zip
• The Manual LC-3!
• Your friendly TAs (Office Hours, Piazza, etc.)
• Textbook
• Appendix on Datapath Control Signals in this PDF.

3 Setup

The software you will be using for this project and all future circuit based assignments is called CircuitSim an interactive circuit simulation package.

In order to use CircuitSim, you must have Docker up and running. If you do not have Docker, follow the instructions laid out in the installation guide found under Canvas Files Docker. Make sure you are using the updated docker container!! The docker-script should automatically do this when you run it. Check by ensuring that the version of CircuitSim in the docker container is version

1.8.2

CircuitSim comes pre-installed on the Docker image, and should be accessible via the desktop. Please only use the CircuitSim through Docker to build your circuits as it is the correct version. CircuitSim downloaded elsewhere may not be compatible with our grader. You have been warned.

CircuitSim is a powerful simulation tool designed for educational use. This gives it the advantage of being a little more forgiving than some of the more commercial simulators. However, it still requires some time and effort to be able to use the program efficiently.

Please do not move or rename any of the provided circuits/elements. You should only be modifying the contents of the ALU, PC, and CC-Logic. The only things you need to modify outside of that is RAM/ROM contents and using the pins/buttons provided

4 Deliverables

Please submit the follow files:

1. sim
2. sim
3. xlsx

to Gradescope under the assignment Project 2.

Note: The autograder may not reflect your final grade on this assignment. We reserve the right to update the autograder as we see fit when grading.

5 Demos

This project will be demoed. The demos will be ten minutes long and will occur in the College of Computing. Stay tuned for details as the due date approaches.

• Sign up for a demo time slot via Canvas before the beginning of the first demo slot. This is the only way you can ensure you will have a slot.
• If you cannot attend any of the predetermined demo time slots, e-mail the Head TA before the beginning of the first demo slot.
• If you know you are going to miss your demo, you can cancel your slot on Canvas with no penalty. However, you are not guaranteed another time slot. You cannot cancel your demo within 24 hours or else it will be counted as a missed demo.
• Your overall project score will be ((project_score * 0.5) + (demo_score * 0.5)). If you miss your demo you will not receive any of these points and the maximum you can receive on the project is 50%.
• You will be able to makeup ONE of your demos at the end of the semester for half credit.
• This grading policy is harsh, but it ensures you understand your own [project].