LumiNUS Open Discussion Question: D1. Refer to the following two MIPS instructions:Assume that the instruction at label “finish” in (ii) is three instructions after bne.For each of the above two instructions, do the following:Questions 1 and 2 refer to the complete datapath and control design covered in lectures #11 and #12. Please use the diagram in Lecture #12 slide 29 or in the COD MIPS 4th edition textbook, Figure 4.17. For your convenience, Lecture #12 slide 29 is also included at the end of this tutorial sheet.For each instruction encoding, do the following:X. [Wr = Write; Rd = Read; M = Mem; R = Reg] Give the estimated latencies for the following MIPS instructions: What do you think the cycle time should be for this particular processor implementation?Hint: First, you need to find out the critical path of an instruction, i.e. the path that takes the longest time to complete. Note that there could be several parallel paths that work more or less simultaneously.Mr. De Blunder made a huge mistake while making his own non-pipelined MIPS processor. He accidentally swapped the two input ports for the RegDst multiplexer: For each of the following instructions, give:If there is no suitable answer, please indicate “No Answer”.
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