D1. Refer to the following two MIPS instructions:

1. add $t0, $s0, $s1 ii. bne $24, $25, finish

Assume that the instruction at label finish in (ii) is three instructions after bne.

For each of the above two instructions, do the following:

• Write out the instruction in hexadecimal representation.
• What are the values of the following control signals: RegDst, RegWrite, and Branch?
• What is the register number supplied to the register files Read Register 1 (RR1) input? How about Read Register 2 (RR2)? Are these registers contents utilized in the ALU stage?
• What is the register number supplied to the register files Write register (WR) input? Is this register actually written?

The answers for (i) are given below.

(a) $t0 = $8; $s0 = $16; $s1 = $17 add $t0, $s0, $s1:

000000 10000 10001 01000 00000 100000 = 0x02114020

(b)

(c)

(d)

Tutorial Questions

Questions 1 and 2 refer to the complete datapath and control design covered in lectures #11 and #12. Please use the diagram in Lecture #12 slide 29 or in the COD MIPS 4^th edition textbook, Figure 4.17. For your convenience, Lecture #12 slide 29 is also included at the end of this tutorial sheet.

1. Let us perform a complete trace to understand the working of the complete datapath and control implementation. Given the following three hexadecimal representations of MIPS instructions:
2. 0x8df80000: lw $24, 0($15) ii. 0x1023000C: beq $1, $3, 12 iii. 0x0285c822: sub $25, $20, $5

For each instruction encoding, do the following:

1. Fill in the tables below. The first table concerns with the various data (information) at each of the datapath elements, while the second table records the control signals generated. Use the notation $8 to represent register number 8, [$8] to represent the content of register number 8 and Mem(X) to represent the memory data at address

X.

[Wr = Write; Rd = Read; M = Mem; R = Reg]

1. Indicate the value of the PC after the instruction is executed.

2. With the complete datapath and control design, it is now possible to estimate the latency (time needed for a task) for the various type of instructions. Given below are the resource latencies of the various hardware components (ps = picoseconds = 10^-12 second):

Give the estimated latencies for the following MIPS instructions:

• SUB instruction (e.g. sub $25, $20, $5)
• LW instruction (e.g. lw $24, 0($15))
• BEQ instruction (e.g. beq $1, $3, 12)

What do you think the cycle time should be for this particular processor implementation?

Hint: First, you need to find out the critical path of an instruction, i.e. the path that takes the longest time to complete. Note that there could be several parallel paths that work more or less simultaneously.

3. [AY2013/14 Semester 2 Term Test #2]

Mr. De Blunder made a huge mistake while making his own non-pipelined MIPS processor. He accidentally swapped the two input ports for the RegDst multiplexer:

For each of the following instructions, give:

1. One example where the incorrect processor still gives the right execution result. ii. One example where the incorrect processor gives the wrong execution result.

If there is no suitable answer, please indicate No Answer.

• add (Addition)
• lw (Load Word)

beq (branch-if-equal), provide the branch offset as immediate value