[SOLVED] CS mips computer architecture 2:

2:
Ziad Matni, Ph.D.
Dept. of Computer Science, UCSB
CPU
Single Cycle
Datapaths
CS 154: Computer Architecture Lecture #12
Winter 2020

Administrative
Talk next week must attend Details to follow
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Reviewing Your Midterm Exams
You can review your midterm with a TA during office hours
Last name: A thru L George T. Tu 10:30 am 12:30 pm
Lastname: MthruZ SidS. Mo3:00pm5:00pm
If you cant go to these o/hs, you can see me instead, but let me know
many days ahead of time first so I can get your exam from the TA
When reviewing your exams:
Do not take pictures, do not copy the questions
TA cannot change your grade
If you have a legitimate case for grade change, the prof. will decide Legitimate = When we graded, we added the total points wrong
Not legitimate = Why did you take off N points on this question????
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Lecture Outline
A Simplified Datapath for all Instructions Single Cycle
ALU Design and Control
FYI: Read the appendix section B.5 (pp. B-26 thru B-38) for review / reference
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Load/Store Instructions
Read register operands
Calculate address using 16-bit offset (immediate) First take the offset and sign-extend it to 32-bits
Then use ALU
Load: Read memory and update register Store: Write register value to memory
Well also need
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includes lw, sw
e.g.: lw $t0, 4($sp)

Branch Instructions
Read register operands Compare operands
Use ALU, subtract
and check Zero output
Calculate target address
Sign-extend displacement
Shift left 2 places
AddtoPC+4 (already calculated by instruction fetch)
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includes beq, bne
e.g.: beq $t1, $t2, Label
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Putting the Elements Together
These simple data paths perform
one instruction in one clock cycle
Each datapath element can only do one function at a time
Hence, we need separate instruction and data memories
In the next lesson(s), we will see how we can perform parallel-like processing, i.e. pipelining
Use multiplexers where alternate data sources are used for different instructions
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R-Type / Load/Store Datapath
EXAMPLE:
sub $t0, $t1, $t2
R[rd] = R[rs] R[rt]
rs = $t1 code rt = $t2 code
rd = $t0 code
rs rt
sub
0
rt
rt
X
rs
rs rt
X 0 rs rt
0
1
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rs rt

R-Type / Load/Store Datapath
EXAMPLE:
sw $t0, 0($t1)
R[rs]+SignExtImm = R[rt]
rs = $t1 code rt = $t0 code
add
1
rt
0 0
Immed (0)
in 32 b
rs
Immed (0) in 16 b
1
0
rt
rs + 0
Value @
(rs + 0) = rt X
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R-Type / Load/Store Datapath
EXAMPLE:
lw $t0, 0($t1)
R[rt] = R[rs]+SignExtImm
rs = $t1 code rt = $t0 code
Value at (rs + 0) from mem.
1
add
1
X
0
0
Immed (0)
in 32 b
Value at (rs + 0)
rs
rs + 0
Value @ (rs + 0)
1
Immed (0) in 16 b
0
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from memory
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Full Datapath (add Jump)
PCold
PCnew
1
EXAMPLE:
j label
PC = JumpAddr
PCnew = (PCold + 4)
+ label * 4
PCold
PCold + 4
PCold + 4
label label * 4
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label
PCnew

What Does This Logic Block Do?
AB
OP
S
0 1
Y OUT
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What Does This Logic Block Do?
Ainv Binv OP[1:0] Result
0
0
00
AND
1
1
00
NOR
0
1
00
A.!B^
1
0
00
!A.B^
0
0
01
OR
1
1
01
NAND
0
0
10
add
0
1
10
subtract*
^ Unpopular combo not used much * To do this, Cin has to be 1
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What Does This Logic Block Do?
Ainv Binv OP[1:0] Result
0
0
00
AND
1
1
00
NOR
0
0
01
OR
1
1
01
NAND
0
0
10
add
0
1
10
subtract
X
1
11
less*
* less: as in a flag for set-if-less-than. Note that Binv has to be 1 when using this
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What Does This Logic Block Do?
Same as previous block, but now with
overflow detection
and with another output, set, used only with slt
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A 32-bit ALU Using 1-bit ALUs as building blocks
Important Notes/Observations:
1. slt and overflow are decisions made in bit 31 (MSB)
2. Bits CarryIn and Binvert work the same way (redundant) and so can be combined into one bit called Bnegate
3. To support branching ops, we need an equality function. This can be done by doing subtraction and seeing if the result is zero(i.e. a=bab=0)
So, we need an output that says the answer at the Result is Zero.
Best done as:
Zero = (Result1 + Result2 + + Result31)
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MIPS ALU Control
ALU when used for
Load/Store:
Branch:
R-type:
ALU_CONTROL[3:0] is Ainv, Bnegate, OP1, OP0 (in that order)
F = add
F = subtract
F depends on funct field
ALU_CONTROL[3:0]
FUNCTION
0000
AND
0001
OR
0010
add
0110
subtract
0111
set-on-less-than
1100
NOR
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Generating the ALU_Control
We get ALUOp from a decode of the opcode field of the instruction
We can further refine choices by looking at funct field
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The Main Control Unit
Control signals derived (i.e. decoded) from instruction
opcode
always read
write
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write
sign extend and add

Full Datapath showing 7 Control Signals
See Fig. 4.16 in book (p.264) for a description of each signal
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YOUR TO-DOs for the Week
Lab 6 due soon
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