[SOLVED] CS computer architecture c/c++ mips CPU Instructions and Procedure Calls

CPU Instructions and Procedure Calls
CS 154: Computer Architecture Lecture #5
Winter 2020
Ziad Matni, Ph.D.
Dept. of Computer Science, UCSB

Administrative
Lab 02 due today! Lab 03 stay tuned
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Lecture Outline
MIPS instruction formats
Refresher on some other MIPS instructions and
concepts
Reference material from CS64 Ill be going over this a little fast
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.data
name: .asciiz Lisa speaks rtn: .asciiz languages!
age: .word 7
Example
What does this do?
.text
main:
syscall
la $t2, age
lw $a0, 0($t2)
li $v0, 1
syscall
li $v0, 4
la $a0, rtn
syscall
li $v0, 10
syscall
li $v0, 4
la $a0, name
# la = load memory address
What goes in here?a
What goes in here?a
4

.data Declaration Types
w/ Examples
var1: var2: var3: num1: num2: str1: str3: str2:
.byte 9
.half 63
.word 9433
.float 3.14
.double 6.28
.ascii Text
.asciiz Text # declare .space 5 # reserve
# declare # declare # declare # declare # declare # declare
a single byte with value 9
a 16-bit half-word w/ val. 63 a 32-bit word w/ val. 9433 32-bit floating point number 64-bit floating pointer number a string of chars
a null-terminated string
5 bytes of space (useful for arrays)
These are now reserved in memory and we can call them up by loading their memory address into the appropriate registers.
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Integers in MIPS
Unsigned 32-bits
Range is 0 to +232 1 (or +4,294,967,295)
Remember positional notation!
For when converting to decimal remember LSB is
position 0
Example: What is 0x00881257 in decimal? Answer:7+24 +26 +29 +212 +219 +223 =8,917,591
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Integers in MIPS
Signed (2s Complement) 32-bits Range is -231 to +231 1
Remember the 2s complement formula! Negate all bits and then add 1
Example: What is 0xFFFE775C in decimal?
Answer: negative 0x000188A4
=-(4+25 +27 +211 +215 +216)
= -10,0516
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Signed Integers in MIPS
Some specific numbers
0:
1:
Most-negative:
Most-positive: 0111 1111 1111
0000 0000 0000 1111 1111 1111 1000 0000 0000
Representing a number using more bits
You want to preserve the numeric value
Example: +6 in 4-bits (0110) becomes 00000110 in 8-bits
Example: -6 in 4-bits (1010) becomes 11111010 in 8-bits
When does this happen in MIPS? Think of I-type instructions
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MIPS Instructions: Syntax

op : operation
rd : register destination rs : register source
rt : register target

op : operation
rs : register source rt : register target
, , , , immed
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MIPS Instruction Formats
Recall:
There are three different instruction formats: R, I, J
ALL core instructions are 32 bits long 6b5b5b5b5b6b
R-Type I-Type
6b 5b 5b 16b
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Instruction Representation in R-Type
The combination of the opcode and the funct code tell the processor what it is supposed to be doing
Example:
op
0
rs
17
rt
18
rd
8
shamt
0
funct
32
op = 0, funct = 32 (0x20) rs = 17
rt = 18
rd = 8
means add means $s1 means $s2 means $t0
shamt = 0
means this field is unused in this instruction
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add $t0, $s1, $s2
0x02324020

Instruction Representation in I-Type
Example:
0x2208007C
op
8
rs
16
rt
8
address/const
124
op = 8
rs = 16
rt = 8
address/const = 124 (0x007C)
mean addi
means $s0
means $t0
is the 16b immediate value
addi $t0, $s0, 124
Worth checking out: https://www.eg.bucknell.edu/~csci320/mips_web/ 1/22/20 Matni, CS154, Wi20 12

Pseudoinstructions
Instructions that are NOT core to the CPU
Theyre macros of other actual instructions
Often they are slower (higher CPI) than core instructions
Examples:
li $t0, C
Is a macro for:
lui $t0, C_hi
ori $t0, $t, C_lo
move $t0, $t1
Is a macro for:
addu $t0, $zero, $t1
https://github.com/MIPT-ILab/mipt-mips/wiki/MIPS-pseudo-instructions has more examples
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Bitwise Operations
Operation
C/C++
MIPS
Shift left
<<sllShift right>>
srl, sra
Bitwise AND
&
and, andi
Bitwise OR
|
or, ori
Bitwise NOT
~
nor*
Bitwise XOR
^
xor
* Specifically, nor $t0, $t0, 0 is equivalent to not(t0)
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Conditional Operations
Branch to a labeled instruction if a condition is true Otherwise, continue sequentially
beq rs, rt, L1 often used with slt, slti if (rs == rt) branch to instruction labeled L1;
bne rs, rt, L1 often used with slt, slti if (rs != rt) branch to instruction labeled L1;
MIPS also has the pseudoinstructions: ble, blt, bge, bgt But pseudoinstructions run slower
j L1
Unconditional jump to instruction labeled L1
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Example
C/C++ code: while (save[i] == k) i += 1;
Given: var i in $s3, k in $s5,
address of save in $s6
In MIPS: Loop:
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sll $t1, $s3, 2 add $t1, $t1, $s6 lw $t0, 0($t1)
bne $t0, $s5, Exit addi $s3, $s3, 1
j Loop
Exit:

Procedure Calls (aka Calling Functions)
Procedure call: jump and link
jal FunctionLabel
Address of following instruction put in $ra Jumps to target address
Procedure return: jump register jr $ra
Copies $ra to program counter
Can also be used for computed jumps
e.g., for case/switch statements
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Calling Nested or Recursive Functions
What happens when you have a saved return address in $ra. and then you call ANOTHER function?
We have to use a standardized way of calling functions The MIPS Calling Convention
Especially important when different dev. teams are making different functions in a project
Also simplifies program testing
Some registers will be presumed to be preserved across a call ;
Others will not
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The MIPS Calling Convention In Its Essence
Remember: Preserved vs Unpreserved Regs
Preserved: $s0 $s7, and $ra, and $sp (by default) Unpreserved: $t0 $t9, $a0 $a3, and $v0 $v1
Values held in Preserved Regs immediately before a function call MUST be the same immediately after the function returns.
Use the stack memory to save these
Values held in Unpreserved Regs must always be assumed to change after a function call is performed.
$a0 $a3 are for passing arguments into a function $v0 $v1 are for passing values from a function
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YOUR TO-DOs for the Week
Readings!
Chapters 2.10 2.13
Stay Tuned for Lab Assignment! Will be announced on Piazza
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