[SOLVED] CS代考计算机代写 data structure cache Carnegie Mellon

Carnegie Mellon
Page Tables
 A page table is an array of page table entries (PTEs) that maps virtual pages to physical pages.
 Per-process kernel data structure in DRAM
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
Physical page number or disk address
Physical memory (DRAM)
PP 0 PP 3
Virtual memory (disk)
0
null
1
1
0
1
0
null
0
1
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
1

Carnegie Mellon
Page Hit
 Page hit: reference to VM word that is in physical memory (DRAM cache hit)
Virtual address
PTE 0
Physical page number or disk address
Physical memory (DRAM)
PP 0 PP 3
Virtual memory (disk)
VP 1
VP 2
VP 7
VP 4
Valid
1
0
1
null
0
0
PTE 7
null
0
1
1
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
2

Carnegie Mellon
Page Fault
 Page fault: reference to VM word that is not in physical memory (DRAM cache miss)
Virtual address
PTE 0
Physical page number or disk address
Physical memory (DRAM)
PP 0 PP 3
Virtual memory (disk)
VP 1
VP 2
VP 7
VP 4
Valid
1
0
1
null
0
0
PTE 7
null
0
1
1
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
3