[SOLVED] CS computer architecture Java compiler RISC-V mips x86 Lecture 2a:

Lecture 2a:
Instructions: Language of the Computer (1/3)
John Owens
Introduction to Computer Architecture UC Davis EEC 170, Winter 2021

Big picture for today
Stored program computer: both programs and information are treated as data
Information: text, pictures, videos, simulation data, etc. All data is stored in the memory of the machine
We wish to manipulate this data:
Some data is instructions; we will treat that data as instructions and execute/evaluate them (but also treat them as data! e.g., linking against other code)
Some data is information; our instructions will operate on this information
Todays topic: What are these instructions?
UC Davis EEC 170, Winter 2021 / John Owens

The instruction set is the most fundamental abstraction in this course.
It is the boundary between software and hardware.
UC Davis EEC 170, Winter 2021 / John Owens

What factors do we want to consider when we are designing our instructions?
UC Davis EEC 170, Winter 2021 / John Owens

Instruction Set

The repertoire of instructions of a computer Different computers have different instruction sets
But with many aspects in common
Early computers had very simple instruction sets
Simplified implementation
Many modern computers also have simple instruction sets
Since the 1980s, the dominant philosophy has been toward simpler (reduced, RISC) instruction sets as opposed to complex (CISC)
x86 is an exception, but x86 CPUs are RISC underneath
UC Davis EEC 170, Winter 2021 / John Owens
2.1 Introduction

The RISC-V Instruction Set

Used as the example throughout the book Developed at UC Berkeley as open ISA
Now managed by the RISC-V Foundation (riscv.org) Typical of many modern ISAs
See RISC-V Reference Data tear-out card Increasing market!
Its a good ISA
Its also ~free
Similar ISAs have a large share of embedded core market
Applications in consumer electronics, network/storage equipment, cameras, printers,
UC Davis EEC 170, Winter 2021 / John Owens

Throughout this discussion: What decisions did the
architects make about the RISC-V instruction set? Why did they make these decisions?

UC Davis EEC 170, Winter 2021 / John Owens

Arithmetic Operations
Add and subtract, three operands
Two sources and one destination

All arithmetic operations have this form
Design Principle 1: Simplicity favors regularity
Regularity makes implementation simpler
Simplicity enables higher performance at lower cost
add a, b, c// a gets b + c
What are a, b, and c?
addonly operates on integer data (whats an integer?) Note: RISC V instructions put the destination first
UC Davis EEC 170, Winter 2021 / John Owens
2.2 Operations of the Computer Hardware

Arithmetic Example C code:
f = (g + h) (i + j);
Compiled RISC-V code:
add t0, g, h
add t1, i, j
sub f, t0, t1
// temp t0 = g + h
// temp t1 = i + j
// f = t0 t1
Were not done yet thoughwhere are t0, g, etc.?
UC Davis EEC 170, Winter 2021 / John Owens

Load Half Unsigned
I LHU
rd,rs1,imm
L{W|D}U
rd,rs1,imm
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Stores Store Byte S SB rs1,rs2,imm Atomic Read Store Halfword S SH rs1,rs2,imm Change Lev
RISC-V Reference Card
StoreWord S SW rs1,rs2,imm S{D|Q} rs1,rs2,imm Environ Shifts Shift Left R SLL rd,rs1,rs2 SLL{W|D} rd,rs1,rs2 Envi
Google it to find it
Shift Right Immediate I SRLI rd,rs1,shamt SRLI{W|D} rd,rs1,shamt Hypervisor Tr
Load Halfword I LH rd,rs1,imm Atomic Read & Set Bit CSRRS rd,csr,rs1 Load Word I LW rd,rs1,imm L{D|Q} rd,rs1,imm Atomic Read & Clear Bit CSRRC rd,csr,rs1
Shift Left Immediate I SLLI rd,rs1,shamt SLLI{W|D} rd,rs1,shamt Trap Redire
ift
Shift Right Arith Imm
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Shift Right R SRL rd,rs1,rs2 SRL{W|D} rd,rs1,rs2 Redirect Tr
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Base Integer Instructions: RV32I, RV64I, and RV128I RV Privileged Instructions Category Name Fmt RV32I Base +RV{64,128} Category Name RV mnemonic Loads Load Byte I LB rd,rs1,imm CSR Access Atomic R/W CSRRW rd,csr,rs1
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b
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a
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c
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it
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Load Byte Unsigned I
Load Half Unsigned I LHU rd,rs1,imm L{W|D}U rd,rs1,imm Atomic Read & Set Bit Imm CSRRSI rd,csr,imm
o yRouSrRAexamrd,srs1,rs2 SRA{W|D} rd,rs1,rs2 Interrupt
LBU rd,rs1,imm
I SRAI rd,rs1,shamt SRAI{W|D} rd,rs1,shamt MMU S
Stores Store Byte S SB rs1,rs2,imm Atomic Read & Clear Bit Imm CSRRCI rd,csr,imm Change Level Env. Call ECALL
L{W|D} rd,rs1,rs2 Environment Return ERET
r
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OR Immediate I ORI rd,rs1,imm
SP CI C.
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ADD is an R type instruction (you dont know this yet)
-mpare Set< R SL(source 2). The r means register.ReaD CYCLE upper Half I RDCYCLEH rd Set < Imm Unsigned I SLTAIUDDrd,rs1,imm ReaD TIME I RDTIME rdSLLIrd,rd,immNSTRBranches Branch = SB BEQ rs1,rs2,immJump Register CR C.JR rd,rs1 JALR x0,rs1,0Store Quad CS C.SQ rs11 ORI,r rd, What this says:OR Immediate I ORI rd,rs1,imm Load Double SP CI C.LDSP rd,AND Immediate I ANDI rd,rs1,immSW rs1,rs2,imm*4CL C.LD rdCompare Set < R SLT rd,rs1,rs2 OR R OR rd,rs1,rs2LQ rd,sp,imm*16s rs2 1,immLI{W|D} rd,rs1,shamt Trap Redirect to SupervisorMRTS ADDI{W|D} rd,rs1,immL{W|D} rd,rs1,rs2 Redirect Trap to Hypervisor MRTHLI{W|D} rd,rs1,shamt Hypervisor Trap to Supervisor HRTSA{W|D} rd,rs1,rs2 Interrupt Wait for Interrupt WFI SUB{W|D} rd,rs1,rs2AI{W|D} rd,rs1,shamt MMU Supervisor FENCE SFENCE.VM rs1D{W|D}rd,rs1,rs2DI{W|D} rd,rs1,immB{W|D}rd,rs1,rs2dWLoad Double Load Double SP Load Quad Load Quad SPLoad Word SP CL C.LQ rd,rs1,imm CI C.LQSP rd,immCI C.LWSP rd,LQ rd,rs1,imm*16SW rs2,sp,imm*4 Set < Imm Unsigned I SLTIU rd,rs1,imm Store Double SP CSS C.SDSP rs2,imm SD rs2,sp,imm*8AND R ANDAND Immediate I ANDI rd,rs1,imm Load Quad SP CI C.LQSP rd,Branches Branch = SB BEQ rs1,rs2,imm Store Quad CS C.SQ rs1,rs2,imm SQ rs1,rs2,imm*16ReRETired I RDINSTRET rduad Branch < SB BLT rs1,rs2,imm Arithmetic ADD CR C.ADD rd,rs1rd,rs1,r rs1dQ.LQ rd *16BSB2s2,imm Store Quad SP CSS C.SCranSynch Instr & Data ILoad Upper Imm CI C.LUI rd,imm MoVe CR C.MV rd,rs1LUI rd,immADD rd,rs1,x0ch=BNEQSPrs2,immSQ rBranch Unsigned SB BGEU rs1,rs2,imm ADD Word Imm CI C.ADDIW rd,imm ADDIW rd,rd,imm ADDs operands arerd(destination),rs1(source 1),rs2Co- SUB is ~the same asrsoCS,Set < Immediate I SLTI rd,rs1,imm.Store Word SP CSS C.SWSP rs2Set < Unsigned R SLTUCounters ReaD CYCLE I RDCYCLE rd Shifts Shift Left Imm CI C.SLLI rd,immCSaD ISystemBIrd,rs1,rs2us1 CREAKSBREAKC.SUBrd,rs1SUBrd,rd,rJrd,imm*1C.ADDI16SP x0,immADDIsp,sp,imm*16s ,rBranch SB BGE rs1,rs2,imm ADD Word CR C.ADDW rd,rs1 ADDW rd,rd,immBranch < Unsigned SB BLTU rs1,rs2,imm ADD Immediate CI C.ADDI rd,imm ADDI rd,rd,immTJump & Link Register UJ JALR rd,rs1,immrdSynch Synch thread I FENCE,r System System CALL I SCALLsCSW rs1 .SD rs1Jump & LinkJ&UJ6 CILADDSrs FENCE.IAL 1rdm 2JumpReaD INSTR upper Half I RDINSTRETH rd Jump & Link J&L CJ C.JAL immReaD TIME upper Half I RDTIMEH rdBranch = SB BNE rs1,rs2,imm32-bit Instruction Formats 16-bit (RVC) Instruction FormatsBranch < SB BLT rs1,rs2,imm Arithm CR C.ADD R CII CSSBranch SB BGE rs1,rs2,immS CIWADD Word CR C.ADDWBranch < Unsigned SB BLD Immediate CI C.ADDISB CLUUC Davis EEC 170, Winter 2021 / John OwensTU rs1,rs2,imm ADSteoLoaAtomic R/W Imm CSRRWI rd,csr,imm Arithmetic ADD ADD Immediate SUBtractLoad Upper Imm Add Upper Imm to PCR I RU USUBrd,RA 11,rs2 SR 2Store Halfword S SH rs1,rs2,imm Store Word S SW rs1,rs2,imm S{ ADD rd,rs1,rs2Shifts Shift Left RSLL rd,rs1,rs2 SLShift Left Immediate I SLLI rd,rs1,shamt SL ADDI rd,rs1,immShift Right Shift Right ImmediateR SRL rd,rs1,rs2 SR I SRLI rd,rs1,shamt SRs Arithmetic ADD R ADD,rsShift Right ArRithmetShift Right Arith ImmADD Immediate I ADDIrd,rs1,rs2 AD rd,rs1,imm AD rd,rs1,rs2 SUrd,immrd,imm CicSrd,rsrI SRAI rd,rs1,shamt SR LUI rd,imm SUBtract R SUBLoad Upper Imm U LUI AUIPC rd,immAdd Upper Imm to PC U AUIPC D|Q} rs1,rs2,imm Environment Breakpoint EBREAK ADD{W|D} rd,rs1,rs2Optional Compressed (16-bit Logicalategory Name Fmt RVCLoads Load Word CL C.LW rd,rs1,immRVI equivalentXOR R XORXOR Immediate I XORI rd,rs1,immAND R AND rd,rs1,rs2LoCLLogicalXOR R XOR rd,rs1,rs2ord CL C.LD rd,rs1,immLW rd,rs1,imm*4Optional Compressed (16-bit) Instruction Extension: RVCCategory Name Fmt RadsLordLWCI C.LDSP rd,immStores Store Word CS C.SW rs1,rs2,imm Load DoubleSet < Immediate I SLTI rd,rs1,imm Store Word SP CSS C.SWSP rs2,immSet < Unsigned R SLTU rd,rs1,rs2 Store Double CS C.SD rs1,rs2,imm SD rs1,rs2,imm*8oSPrd,immLW rd,sp,imm*4adWeADD SP Imm * 4 CIW C.ADDI4SPN rd’,imm ADDI rd’,sp,imm*4P ImStrWLoad Immediate CI C.LI rd,imm ADDI rd,x0,immJump & Link Register System Env. BREAKCR C.JALRCSS C.SQSP rs2SUB CR SSCIC.EBREAKEBREAKCStotbleoreQuad SPre Detic ADD CRooBranches Branch=0 CB C.BEQZ rs1,imm BEQ rs1′,x0,immStore Double SP CSS C.SDSP rs2Branch=0 CB C.BNEZ rs1,imm BNE rs1′,x0,imm Jump CJ C.J imm JAL x0,immrs1LD rd,rs1,imm*8LD rd,sp,imm*8CLs2,ADD rd,rd,rs1JAL ra,immJALRra,rs1,0sp,imm Register Operands RISC-V has a 32 64-bit register file- Use for frequently accessed data- 64-bit data (in RISC-V) is called a doubleword- 32 64-bit general purpose registers x0 to x31- x0 is hardwired to 0- 32-bit data is called a wordWhere is the data stored?Arithmetic instructions use register operands- Important! In RISC-V, all arithmetic instructions ONLY use register operandsDesign Principle 2: Smaller is faster- c.f. main memory: millions of locationsUC Davis EEC 170, Winter 2021 / John Owens2.3 Operands of the Computer Hardware RISC-V Registers x0: the constant value 0 x1: return address x2: stack pointer x3: global pointer x4: thread pointer x5 x7, x28 x31: temporaries x8: frame pointer x9, x18 x27: saved registers x10 x11: function arguments/results x12 x17: function argumentsUC Davis EEC 170, Winter 2021 / John Owens Register Operand Example C code:f = (g + h) – (i + j);- f, …, j in x19, x20, …, x23 Compiled RISC-V code:add x5, x20, x21add x6, x22, x23sub x19, x5, x6UC Davis EEC 170, Winter 2021 / John Owens Memory Operands (architectural decisions) Main memory used for composite data – Arrays, structures, dynamic data To apply arithmetic operations:- Load values from memory into registers- Store result from register to memory Memory is byte addressed- Each address identifies an 8-bit byte- Support for byte [8b], halfword [16b], word [32b], doubleword [64b] RISC-V is Little Endian- Least-significant byte at least address of a word [processors]- c.f. Big Endian: most-significant byte at least address [network] RISC-V does not require words to be aligned in memory- Unlike some other ISAshttps://en.wikipedia.org/wiki/Endianness UC Davis EEC 170, Winter 2021 / John Owens Memory Operand Example C code:A[12] = h + A[8];- h in x21, base address of A in x22 Compiled RISC-V code:- Index 8 requires offset of 64 – 8 bytes per doublewordld dest, imm(src): dest: destination register imm: immediate (integer) src: base memory address, in register ld x9, 64(x22)// x9 <- Mem[x22 + 64]addx9, x21, x9sd x9, 96(x22)// Mem[x22 + 96] <- x9UC Davis EEC 170, Winter 2021 / John Owens Registers vs. Memory Registers are (much) faster to access than memory Operating on memory data requires loads and stores- More instructions to be executed Compiler must use registers for variables as much as possible- Only spill to memory for less frequently used variables- Register optimization is important!UC Davis EEC 170, Winter 2021 / John Owens Immediate Operands ConstantdataspecifieFdrineaenin&struOctpioennBase Integer Instructions: RV32I, RV64I, and RV128I Category Name Fmt RV32I Base +RV{64,128}addi x22, x22, 4// add the number 4 toLoads Load Byte I LB rd,rs1,imm- Small constants are commonLoad Halfword I LH rd,rs1,imm// x22, store back in x22Load Word Load Byte Unsigned Load Half UnsignedI LW I LBU I LHUrd,rs1,immrd,rs1,immrd,rs1,immrs1,rs2,immrs1,rs2,immrs1,rs2,immL{D|Q}L{W|D}US{D|Q}rd,rs1,immrd,rs1,immrs1,rs2,imStores Store Byte S SB Make the common case fastStore Halfword S SH Store Word S SWShifts Shift Left R SLLShift Left Immediate I SLLI rd,rs1,shamtrd,rs1,rs2rd,rs1,shard,rs1,rs2rd,rs1,shard,rs1,rs2rd,rs1,sha- Immediate operand avoids a load instructionShift Right R SRL rd,rs1,rs2 Shift Right Immediate I SRLI rd,rs1,shamtShift Right Arithmetic R SRA rd,rs1,rs2Shift Right Arith ImmI SRAI rd,rs1,shamtrd,rs1,rs2SLL{W|D}SLLI{W|D}SRL{W|D}SRLI{W|D}SRA{W|D}SRAI{W|D}ADD{W|D}rd,rs1,rs2ADDI{W|D} rd,rs1,immSUB{W|D}rd,rs1,rs2 Arithmetic ADD ADD Immediate SUBtractLoad Upper Imm Add Upper Imm to PCR I RU U ADD rd,rs1,rs2ADDIrd,rs1,immSUB rd,rs1,rs2LUI rd,immAUIPC rd,imm LogicalXOR R XOR rd,rs1,rs2Optional ComprCategory Name FLoads Load Word C UC Davis EEC 170, Winter 2021 / John Owens XOR Immediate I XORI rd,rs1,immmm m memL Load Word SP CIUnsigned Binary Integers Given an n-bit numbern1 n2 1 0 x=xn12 +xn22 +!+x12 +x02Range: 0 to +2n 1 Example- 0000 0000 … 0000 10112= 0231 + … + 123 + 022 +121 +120 = 0 + … + 8 + 0 + 2 + 1 = 1110 Using 64 bits: 0 to +18,446,774,073,709,551,615UC Davis EEC 170, Winter 2021 / John Owens2.4 Signed and Unsigned Numbers Numbers Bits are just bits (no inherent meaning)- conventions define relationship between bits and numbers Binary numbers (base 2)- 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001… – decimal: 0 .. 2n-1 Of course it gets more complicated:- numbers are finite (overflow)- fractions and real numbers- negative numbers- RISC-V restrictions (e.g., no RISC-V subi instruction; addi can add a negative number) How do we represent negative numbers?- i.e., which bit patterns will represent which numbers?UC Davis EEC 170, Winter 2021 / John Owens Possible Representations Sign Magnitude 000 = +0001 = +1 010 = +2 011 = +3 100 = -0 101 = -1 110 = -2 111 = -3One’s Complement 000 = +0001 = +1010 = +2011 = +3 100 = -3 101 = -2 110 = -1 111 = -0Two’s Complement 000 = +0001 = +1010 = +2011 = +3 100 = -4 101 = -3 110 = -2 111 = -1 In all these, the most significant bit is the sign bit Issues: balance, number of zeros, ease of operationsUC Davis EEC 170, Winter 2021 / John Owens 2s-Complement Signed IntegersGiven an n-bit numbern1 n2 1 0 x=xn12 +xn22 +!+x12 +x02Range: 2n 1 to +2n 1 1 Example- 1111 1111 … 1111 11002= 1231 + 1230 + … + 122 +021 +020 = 2,147,483,648 + 2,147,483,644 = 410Using 64 bits: 9,223,372,036,854,775,808 to 9,223,372,036,854,775,807UC Davis EEC 170, Winter 2021 / John Owens 2s-Complement Signed Integers Bit 63 (the most significant bit, MSB) is sign bit- 1 for negative numbers- 0 for non-negative numbers(2n 1) cant be representedNon-negative numbers have the same unsigned and 2s- complement representationSome specific numbers- 0:- 1:- Most-negative:- Most-positive:0000 0000 … 0000 1111 1111 … 1111 1000 0000 … 0000 0111 1111 … 1111UC Davis EEC 170, Winter 2021 / John Owens Signed NegationComplement and add 1– Complement means flip all the bitsComplement means 1 0, 0 1 x+x=1111…111 =1 2x +1= x -Example: negate +2- +2 = 0000 0000 … 0010two- 2 = 1111 1111 … 1101two + 1 = 1111 1111 … 1110twoUC Davis EEC 170, Winter 2021 / John Owens Sign Extension Representing a number using more bits – Preserve the numeric valueReplicate the sign bit to the left- c.f. unsigned values: extend with 0sExamples: 8-bit to 16-bit- +2: 0000 0010 => 0000 0000 0000 0010
2: 1111 1110 => 1111 1111 1111 1110
Base Integer Instructions: RV32I, RV64I, and RV128I
Category
Name Fmt
RV32I Base
rs1,rs2,imm
rs1,rs2,imm
rs1,rs2,imm
rd,rs1,rs2
rd,rs1,shamt
rd,rs1,rs2
rd,rs1,shamt
rd,rs1,rs2
rd,rs1,shamt
rd,rs1,rs2
+RV{64,128} Cate CSR
Free & Open
Loads Load Byte Load Halfword Load Word Load Byte Unsigned Load Half Unsigned
I I I I I
LBrd,rs1,imm
LHrd,rs1,imm
LWrd,rs1,imm
LBU rd,rs1,imm
LHU rd,rs1,imm
L{D|Q}rd,rs1,imm
L{W|D}U rd,rs1,imm

In RISC-V instruction set
Stores
Store Byte S SB Store Halfword S SH Store Word S SW
Ato Atom Chan
lb: sign-extend loaded byte Shifts
S{D|Q}
SLL{W|D}
SLLI{W|D}
SRL{W|D}
SRLI{W|D}
SRA{W|D}
SRAI{W|D}
ADD{W|D}
rs1,rs2,imm
rd,rs1,rs2
lbu: zero-extend loaded byte Shift Right R SRL Shift Right Immediate I SRLI
Shift Right Arithmetic R SRA
Shift Right Arith Imm I SRAI Arithmetic ADD R ADD
ADD Immediate I ADDI SUBtract R SUB
rd,rs1,imm ADDI{W|D} rd,rs1,imm
Shift Left R SLL Shift Left Immediate I SLLI
rd,rs1,shamt Trap rd,rs1,rs2 Re rd,rs1,shamt Hyper rd,rs1,rs2 Inter rd,rs1,shamt MMU rd,rs1,rs2
rd,rs1,rs2
SUB{W|D}rd,rs1,rs2
UC Davis EEC 170, Winter 2021 / John Owens
R
g
A
A
m i
E d

Break
UC Davis EEC 170, Winter 2021 / John Owens

Administrative stuff
Im going to aim for a W 8:309:30 office hour (Coffee House) HW1 is out. Questions? Issues? Post on Slack #hw1
Looking at the RARS MIPS-V simulator.
Do you want to run on personal computers or in lab?
Can you run Java?
Slides ran a bit slow this morning! Word vs. Doubleword (sorry)
UC Davis EEC 170, Winter 2021 / John Owens

Representing Instructions

Instructions are encoded in binary Called machine code

RISC-V instructions
How do we get from add x5, x20, x21 to binary?
Encoded as 32-bit instruction words
Big picture: We divide the 32-bit instruction word into fields, each of a few bits, and encode different pieces information from the instruction into each field
Small number of formats encoding operation code (opcode), register numbers,
Regularity!
UC Davis EEC 170, Winter 2021 / John Owens
2.5 Representing Instructions in the Computer

Hexadecimal
Base 16
Compact representation of bit strings
4 bits (nibble) per hex digit
0x means Im hexadecimal
0
0000
4
0100
8
1000
c
1100
1
0001
5
0101
9
1001
d
1101
2
0010
6
0110
a
1010
e
1110
3
0011
7
0111
b
1011
f
1111
Example: 0x eca8 6420
1110 1100 1010 1000 0110 0100 0010 0000
UC Davis EEC 170, Winter 2021 / John Owens

RISC-V R-format Instructions
Instruction fields
opcode: operation code
rd: destination register number
funct3: 3-bit function code (additional opcode)
rs1: the first source register number
rs2: the second source register number
funct7: 7-bit function code (additional opcode)
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
funct7
rs2
rs1
funct3
rd
opcode
UC Davis EEC 170, Winter 2021 / John Owens

R-format Example
add x9,x20,x21
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
funct7
rs2
rs1
funct3
rd
opcode
0
21
20
0
9
51
0000000
10101
10100
000
01001
0110011
0000 0001 0101 1010 0000 0100 1011 0011two = 015A04B316
UC Davis EEC 170, Winter 2021 / John Owens

imm[11:0] imm[11:5] rs2
rs1 funct3 rd
rs1 funct3 imm[4:0] rs1 funct3 imm[4:1|11]
rd rd
opcode opcode opcode opcode opcode
I-type S-type B-type U-type J-type
LUI AUIPC JAL JALR BEQ BNE BLT BGE BLTU BGEU LB
LH LW LBU LHU SB
SH SW ADDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SRAI
SUB
SLL
SLT
Opcode Map
imm[12|10:5] rs2
imm[31:12] imm[20|10:1|11|19:12]
RV32I Base Instruction Set
imm[31:12]
rd
0110111
imm[31:12]
rd
0010111
imm[20|10:1|11|19:12] imm[11:0]
rd
1101111
rs1
000
rd
1100111
imm[12|10:5] imm[12|10:5] imm[12|10:5] imm[12|10:5] imm[12|10:5] imm[12|10:5]
imm[11:0]
rs2
rs1
000
imm[4:1|11] imm[4:1|11] imm[4:1|11] imm[4:1|11] imm[4:1|11] imm[4:1|11] rd
1100011
rs2
rs1
001
1100011
rs2
rs1
100
1100011
rs2
rs1
101
1100011
rs2
rs1
110
1100011
rs2
rs1
111
1100011
rs1
000
0000011
imm[11:0]
rs1
001
rd
0000011
imm[11:0]
rs1
010
rd
0000011
imm[11:0]
rs1
100
rd
0000011
imm[11:0]
rs1
101
rd
0000011
imm[11:5]
rs2
rs1
000
imm[4:0]
0100011
imm[11:5]
rs2
rs1
001
imm[4:0]
0100011
imm[11:5]
rs2
rs1
010
imm[4:0]
0100011
imm[11:0]
rs1
000
rd
0010011
imm[11:0]
rs1
010
rd
0010011
imm[11:0]
rs1
011
rd
0010011
imm[11:0]
rs1
100
rd
0010011
imm[11:0]
rs1
110
rd
0010011
imm[11:0]
rs1
111
rd
0010011
0000000
0100000
shamt
rs1
001
rd
0010011
0000000
shamt
shamt
rs1
rs1
101
101
rd
rd
0010011
0010011
0000000 rs2 rs1 000 rd 0110011 ADD
0100000
rs2
rs1
000
rd
0110011
0000000 rs2 rs1 001
rd 0110011
0000000 rs2 0000000 rs2 0000000 rs2
rs1 010 rs1 011 rs1 100
rd rd rd
0110011
0110011
0110011
SLTU
UC Davis EEC 170, Winter 2021 / John Owens
XOR

RISC-V I-format Instructions
Immediate arithmetic and load instructions
rs1: source or base address register number
immediate: constant operand, or offset added to base address
2s-complement, sign extended
How big can this immediate be?
Why did they pick this size?
Advantages/disadvantages of making it bigger/smaller?
12 bits 5 bits 3 bits 5 bits 7 bits
immediate
rs1
funct3
rd
opcode
UC Davis EEC 170, Winter 2021 / John Owens

RISC-V I-format vs. R-format

I-format:
R-format:
7 bits
12 bits
5 bits
3 bits
5 bits
7 bits
immediate
rs1
funct3
rd
opcode
funct7
rs2
rs1
funct3
rd
opcode
5 bits
5 bits
3 bits
5 bits
7 bits
Design Principle 3: Good design demands good compromises
Different formats complicate decoding, but allow 32-bit
instructions uniformly
Keep formats as similar as possible
UC Davis EEC 170, Winter 2021 / John Owens

RISC-V S-format Instructions
Different immediate format for store instructions
rs1: base address register number
rs2: source operand register number
immediate: offset added to base address
Split so that rs1 and rs2 fields always in the same place
imm[11:5]
rs2
rs1
funct3
imm[4:0]
opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
UC Davis EEC 170, Winter 2021 / John Owens

RISC-V I-format vs. R-format vs. S-format I-format:
immediate
rs1
funct3
rd
opcode
R-format: 7 bits
S-format: 7 bits
5 bits
5 bits
3 bits
5 bits
7 bits
12 bits
5 bits
3 bits
5 bits
7 bits
funct7
rs2
rs1
funct3
rd
opcode
imm[11:5]
rs2
rs1
funct3
imm[4:0]
opcode
5 bits
5 bits
3 bits
5 bits
7 bits
UC Davis EEC 170, Winter 2021 / John Owens