[SOLVED] CS代考计算机代写 cache Registers and Memory

Registers and Memory
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Registers
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Register
á Registers are circuits inside of the processor
á Registers used extensively throughout the datapath
± e.g. adding two numbers. The numbers are temporary stored in the registers and becomes the inputs of ALU

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(General) Register
á General purpose: Store a multibit datum, e.g., byte or word
á Can implement with an array of D flip-flops
4-bit General Register

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á Shifts the stored bits on each clock
á Can be designed to shift left or right
Shift Register
á What can this be useful for?
± Multiplication or division by two
± Conversion between serial and parallel interfaces

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á Thecounterfortheprocessor
á AsetofTflipflop
Count Register
á Countuporcountdown,butwhen?
± Count up toggled on rising-edge
± Count down toggled on falling-edge
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Register Files
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á A collection of registers
á Can read two registers
á Canwriteoneregister
á Write triggered by clock (blue)
á How many bits on different inputs?
Register File
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á Use multiplexor to select which registers to read
Register File – Reading
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á Combinedecoderwith clock using AND to store the write data
Register File – Writing
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Register File with ALU
Instruction
ALU

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RAM Size 16 GB 14
SRAM
static random-access uu}å«2
DRAM
Dynamic random-access memory
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Memory
Specification of Dell G5 Gaming PC
Processor Type 10th Generation Intel Core i7-10700 Processor Speed 2.90 GHz
Processor Cores 8
Processor Cache 16 MB Intel Smart Cache

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SRAM Multiplexor
á SRAM is HUGE and cannot be built like register files
± The multiplexor grows with the number of memory locations
± Giant OR is more realistically implemented with a tree of OR gates

SRAM Multiplexor á Instead,themultiplexorforSRAMis
Data Enable Out 010 111 x0Z
implemented with tri-state buffer
á Tri-state buffer
± Select = 1, output = data
± Select = 0, output = high impedance state á Effectively disconnected
á Denoted Z in truth table
á Only one out is active (or short circuit) COMP273 McGill
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SRAM Multiplexor
Avoid AND array and OR tree with an array of Tri-State buffers
Need carefully design the select signal to avoid short circuits
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YYYXYYYXX
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á May still need a large decoder
á 1 megabit memory would need a
1048576 D Flipflops and Tri-state buffers
20 to 1,048,576 decoder!
D D
3-to-8 decoder
HUGE decoder with over one million outputs! 19
SRAM Decoder
20 AtA20 to
1048576
0 19 1,048,576 decoder
D D
D
1 bit output

YXX
YXX
YXX
YXX
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AtA 10
10 19 1024
A tA
09 1024
0 1 2 YXX1023
10
to 1024
D D D YXXD D D D YXXD D D D YXXD
decoder
10
to 1024
decoder
SRAM Decoder
multiplexor
1048576 D Flipflops and Tri-state buffers Organized in 1024 by 1024 grid
D D D YXXD
Organizing memory in rectangular arrays and use two decoders
20
1 bit output

SRAM Decoder
á How much can we save from 1MB memory á A linear array
± One 20 to 1048576 decoder for all address lines
á A rectangular array
± One 10 to 1024 decoder for the upper address lines ± One 10 to 1024 decoder for the lower address lines
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Multi-bit Access
Multiple memories next to each other. Decoding can be reused!
Example: 4M x 8 bits. Each bit is a 4096 by 1024 array

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Basic 4×2 SRAM
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Multi-bit Access

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á á
Data is stored in D-Latch 4-6 transistors per bit.
á Data is stored in capacitor á Uses 1 transistor per bit.
á Much denser and cheaper.
SRAM
DRAM
DRAM vs SRAM

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SRAM
DRAM
á Data is stored if not overwritten and power is on
á
á
á SLOW
á Fixed access time
á Fast and used for caches
DRAM vs SRAM
Capacitor charge
is not permanent
Refresh consumes 1% to 2% of active cycle

á Registers
± Data registers
± Count registers ± Shift registers
á Memory ± SRAM
± DRAM á Textbook
Review
± B8, B9 of 5th and 6th edition, C7-C10 of 4th edition
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