2/22/2021 Exam1 CMPEN331 Fall2020: Fall2020_Combined_Sections_CMPEN331
This quiz has been regraded; your score was not affected.
Exam1 CMPEN331 Fall2020
Due Oct 6, 2020 at 11:59pm Points 100 Questions 28 Available Oct 6, 2020 at 8pm – Oct 6, 2020 at 11:59pm about 4 hours Time Limit 130 Minutes
Instructions
CMPEN 331 Computer Organization and Design Exam 1
Instructions and Policies
You have 120 minutes to complete this exam.
This exam is open book/open notes, but you may not communicate with anyone other than the instructor and/or TAs and LAs during the exam.
You must keep your camera on during the exam and clearly show your face and immediate surroundings (no virtual backgrounds).
Please turn off all phones, smartwatches, and other mobile devices. Remove all hats & headphones.
Only the textbook, canvas files for class, slides from class, and notes taken printed/handwritten notes are permitted. You may not view any content online or on another device.
Once you begin the exam, you must complete it within the time limit. If you logout of Canvas or close your browser after you enter the exam, the countdown will not stop.
There may be partial credit for incomplete answers; write as much of the solution as you can.
Show all of your work for a problem. Answers without derivations are worth no credit.
Please be sure that all parts of each problem have been completed.
Any kind of cheating may result in failing the course.
General Instructions: Link
This quiz was locked Oct 6, 2020 at 11:59pm.
Attempt History
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2/22/2021 Exam1 CMPEN331 Fall2020: Fall2020_Combined_Sections_CMPEN331
Attempt Time Score Regraded
LATEST Attempt 1 119 minutes 93.5 out of 100 93.5 out of 100
Correct answers are hidden.
Score for this quiz: 93.5 out of 100 Submitted Oct 6, 2020 at 10pm This attempt took 119 minutes.
Question 1
1 / 1 pts
The MIPS addi instruction operates on register values as if they were unsigned integers in binary format.
True False
Question 2
1 / 1 pts
MIPS is a load-store architecture, which means that only load and store instructions access memory.
True False
Question 3
1 / 1 pts
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Question 4
1 / 1 pts
The MIPS architecture has only 32 registers.
True False
Question 5
0 / 1 pts
The MIPS arithmetic instructions (add, addi, etc.) all use sign-extension.
True False
Incorrect
Incorrect
A quantity in memory (byte, halfword, word, double word) is aligned if its memory address is a multiple of its size in bytes.
True False
Question 6
0 / 1 pts
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Question 7
1 / 1 pts
The MIPS procedure call conventions require that a function can only access registers and the memory locations between the stack pointer and the frame pointer.
True False
Question 8
1 / 1 pts
The MIPS add instruction operates on register values as if they were signed integers in 2’s complement format.
True False
The MIPS logical instructions (and, andi, etc.) all use zero-extension.
True False
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Question 10
1 / 1 pts
The MIPS sra instruction is suitable for signed integers in 2’s complement format, since it acts like “divide by a power of 2”.
True False
Question 11
0 / 1 pts
The MIPS sllv instruction has three register operands – a destination, a source (the value to be shifted), and a variable specifying the shift amount.
True False
Incorrect
Question 9
1 / 1 pts
The acronym PC is short for Program Counter.
True False
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Question 12
1 / 1 pts
The MIPS assembler instruction (not pseudo instruction) addi $t1, $t2, 65536
is properly formulated (all fields are in required locations and are valid).
True False
Question 13
1 / 1 pts
The Program Counter indicates how many instructions have been executed.
True False
Question 14
1 / 1 pts
The MIPS procedure call conventions require the first five arguments to be placed in registers $a0, $a1, $a2, $a3, $a4, and any remaining arguments to be placed on the stack.
True
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Question 15
0 / 1 pts
The MIPS processor supports an instruction inc that can increment a value stored in a memory location by one.
True False
Incorrect
Question 16 Original Score: 1 / 1 pts Regraded Score: 1 / 1 pts
This question has been regraded.
One of the MIPS architecture design principles is “Regularity favors
Simplicity”.
True False
Incorrect
Incorrect
False
Question 17
0 / 2 pts
The two MIPS data segments are
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Question 18
2 / 2 pts
What is the final value of $pc after an add instruction?
the current value of $pc (it didn’t change) the current value of $pc + 4
the current value of $pc + 8
none of the above
Static Data and Dynamic Data Stack Data and Heap Data Character Data and Integer Data none of the above
Question 19
2 / 2 pts
The MIPS text segment contains
character strings integer data instructions
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Question 20
2 / 2 pts
Which value is stored in $ra by the jal instruction?
the current value of $pc (address of jal instruction) the current value of $pc + 4
the current value of $pc + 8
none of the above
Question 21
2 / 2 pts
Which of these would not be valid as the address of a MIPS instruction?
0x00400000 0x00400298 0x004002fc
none of the above – they are all valid instruction addresses, assuming the program is long enough
none of the above
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Question 22
16 / 16 pts
3) Short answer. 2 points each.
In parts a – e, write one MIPS assembler instruction; avoid pseudo instructions. Underline the part of the instruction that indicates the addressing mode that you are illustrating.
In parts f – g, the name of the instruction is sufficient; you don’t need to write a complete instruction.
a. Give an example of an instruction that uses Immediate Addressing.
b. Give an example of an instruction that uses Register Addressing.
c. Give an example of an instruction that uses Base (Displacement) Addressing.
d. Give an example of an instruction that uses PC-Relative Addressing. e. Give an example of an instruction that uses Pseudodirect Addressing.
f. Which instruction should be used to load a single byte from memory to a register?
g. In part f, which other instruction could also be used?
h. Explain any differences in behavior between the instructions in parts f and g. [If your answers to parts f and g are right, they will behave differently.]
Your Answer:
a. addi $t0, $t1, 7
b. add $t0, $t1, $t2
c. sw $t0, 16($t1)
d. beq $t0, St1, BLabel e. j JLabel
f. lb g.lbu
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h. The difference is that lb is sign-extension and lbu, where u means “unsigned”, is zero-extension.
Question 23
11 / 12 pts
4) Short answer. 4 points each.
a. For the MIPS R-format instructions, what are the field names, and how many bits do they contain?
______ ______ ______ ______ ______ ______ bits
b. Consider a branch instruction such as bne $t0, $t1, L7
…
L7: …
When the assembler generates machine code for the branch instruction, it must replace the symbol L7 by a number. Describe how this number is calculated.
c. Write a sequence of MIPS instructions to implement the pseudo instruction
ble $t0,$t1, L2 (branch less than or equal to)
Your Answer:
a.
op, rs, rt, rd, shamt, funct
6, 5, 5, 5, 5, 6
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b. The number is calculated by the difference between the number of instructions between the branch and the instruction whose label is L7.
c.
slt $t2, $t1, $t0 beq $t2, $zero, L2
minor mistake in part b.
Question 24
15 / 16 pts
5) Short code sequences. No more than 3 instructions each.
Assume these declarations in C/C++: int Func(int a); int Array[100]; int b;
a. Call a function with one argument. To be specific, translate b = Func(17); assuming b is to be placed in register $s1. For your reference, the instruction li could be used to load an immediate value in a register (e.g. li $a0, constant value).
b. Load the value of Array[j] into register $t1. Assume the base address of Array is already in register $s0, j is already in register $t0, and j is a valid index into Array. [Read part c before writing your answer to part b.]
c. After executing the instructions from part b, in one more instruction, also load the value of Array[j+1] into register $t2. [Partial credit if you use more than one instruction here.]
d. Place the third, fourth and fifth bits of register $t0 into the fourth, fifth and sixth bits of register $t1. Set all the remaining bits of register $t1 to 0.
Your Answer:
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a.
addi $a0, $zero, 17 jal Func
add $s1, $v0, $zer0
b.
sll $t3, $t0, 2 add $t3, $t3, $s0 lw $t1, 0($t3)
c.
lw $t2, 4($t3)
d.
addi $t1, $t0, 0x001c sll $t1, $t1, 1
first instruction in part d should be andi.
Question 25
14 / 15 pts
6) Write everything that you would write as part of a program in MIPS assembler. Pseudo instructions are allowed here. As long as your solution is correct, fewer instructions is better. A few comments may be helpful.
Write a function whose prototype is int sum(unsigned int i); that returns the sum of all numbers from 0 to i.
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Your Answer: .text
.globl sum sum:
addi $sp, $sp -4 sw $s0, 0($sp) move $t0, $zero
Loop:
add $s0, $s0, $t0
addi $t0, $t0, 1
slt $t1, $t0, $a0
bne $t1, $zero, Loop add $v0, $s0, $zero lw $s0 0($sp)
addi $sp, $sp, 4
jr $ra
Question 26
7 / 8 pts
7) Consider a 32-bit hexadecimal number stored in memory as follows:
Address
Value
100
2A
101
C2
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102
08
103
1B
a. (1 point) If the machine is big endian and uses 2’s complement representation for integers, write the 32-bit integer number stored at address 100 (you may write the number in hex).
b. (1 point) If the machine is big endian and the number is an IEEE single- precision floating point value, is the number positive or negative?
c. (2 points) If the machine is big endian and the number is an IEEE single-precision floating point value, determine the decimal equivalent of the number stored at address 100 (you may leave your answer in scientific notation form, as a number times a power of two).
d. (1 point) If the machine is little endian and uses 2’s complement representation for integers, write the 32-bit integer number stored at address 100 (you may write the number in hex).
e. (1 point) If the machine is little endian and the number is an IEEE single-precision floating point value, is the number positive or negative?
f. (2 points) If the machine is little endian and the number is an IEEE single-precision floating point value, determine the decimal equivalent of the number stored at address 100 (you may leave your answer in scientific notation form, as a number times a power of two).
Your Answer: a. 717359131
b. positive
c. (-1)^0*(1+F)*2^(85-127) 3. 447×10^-13
d. 453558826
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e. positive
f. (-1)^0*(1+F)*2^(54-127) 1. 131×10^-22
a nd d are incorrect
Question 27
4.5 / 5 pts
8) Write a MIPS program that always checks the bit 0 of a memory data at address 0x0BF81234. If it is equal to one add nth and (n+1)th elements of an array and store it to memory address 0x0BF85678 . Suppose $t0 contains the address of the 0th element of an array of 32-bit data and $t1 = n.
Your Answer:
.text
.globl func:
addi $t3, $zero, 0x0BF81234 addi $t4, $zero, 0x0BF85678 lw $t2, 0($t3)
andi $t5, $t2, 0x00000001 bne $t5, $zero, L1
j Exit L1:
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sll $t6, $t1, 2 add $t7, $t6, $t0 lw $t8, 0($t7)
lw $t9, 4($t7)
add $t7, $t8, $t9
sw $t7, 0($t4) Exit:
Question 28
6 / 7 pts
9) First, draw the state machine for the following program. Then write the corresponding Verilog behavioral code.
Input: X – 1 bit number
Output: Z – 1 bit number
Clock: clk (State will change at positive edge of the clock)
Output will be equal to one if Xn-2 Xn-1 Xn = 011 or Xn-2 Xn-1 Xn = 101
Your Answer:
module Q28 (x, y, clk); input x, clk;
output Z; reg Z;
parameter S000 = 3’b000, S001 = 3’b001, S010 = 3’b010, S011 = 3’b011, S100 = 3’b100, S101 = 3’b101, S110 = 3’b110, S111 = 3’b111
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reg [2:0] currentState; reg[2:0] nextState;
always @(posegde clk) begin
currentState <= nextState; endalways @(currentState or x) begincase (currentState) S000: beginif (x == 0)nextState <= S001;elsenextState <= S010;endS001: beginif (x == 0)nextState <= S000;elsenextState <= S011;endS010: beginif (x == 0)nextState <= S101;elsehttps://psu.instructure.com/courses/2087674/quizzes/4024190 18/19 2/22/2021 Exam1 CMPEN331 Fall2020: Fall2020_Combined_Sections_CMPEN331Quiz Score: 93.5 out of 100 nextState <= S000; endS011: begin if (x == 0)nextState <= S000; elsenextState <= S000;Z <= 1; endS101: begin if (x == 0)nextState <= S000 elsenextState <= S000Z <= 1 endendcase endmodulehttps://psu.instructure.com/courses/2087674/quizzes/4024190 19/19
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