[SOLVED] CS代写 Computer Organization, Spring 2022

Computer Organization, Spring 2022
LAB 5 : 5-Stage Pipeline Processor
Due : 2022/6/1 23:59
In this lab you should modify the Single Cycle CPU designed from Lab4 and implement a 5-stage Pipeline Processor with IF, ID, EX, MEM and WB stages. For a pipeline processor design, a pipeline register module between each 2 stages is required and the pipeline registers are written when each positive clock edge is triggered. You also need to implement forwarding unit and hazard detection unit.

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2. Attached file
● Lab5Answer(Don’tmodifythesefile)
● Lab5Code(Yourcodeshouldputinhere) ● lab5TestScript.sh
● readme.txt

3. HW Requirement
(1.) Please use the lab5TestScript.sh we provide you. (2.) Please implement below
● ALU_Ctrl.v
● Decoder.v
● Forwarding.v
● Hazard_detection.v ● Imm_Gen.v
● MUX_2to1,3to1.v ● Shift_Left_1.v
● Pipeline_CPU.v
● IFID_register.v
● IDEXE_register.v
● EXEMEM_register.v ● MEMWB_register.v
(3.) Testcase
● Basictestcase(withoutdatadependency)(30%)
● Mediumtestcase(withdatadependency)(40%)
○ Case7~10
● Advancedtestcase(30%)
○ Case11~13
○ Load-use
○ beqandjalinstruction
4. How to test
You can use any HDL simulator(Model Sim / Vivado / ISE), but also need to test your code with lab5TestScript.sh (Only run in UNIX like OS). (TA’s environment : Ubuntu 20.0.4)
❖ We do not answer the bug of HDL simulator
❖ Do not modify *.txt file Command:
$ chmod +x ./lab5TestScript.sh && ./lab5TestScript.sh

● Thelastlineisyourscore
5-Stage Pipeline Processor (80%) Report (20%)
● Detaileddescriptionoftheimplementation ● Implementationresults
● Problemsencounteredandsolutions
❖ Late submission: 10% penalty per day ❖ No plagiarism, or you will get 0 points
6. Hand in
● Zipyourfolderandnameitas “$(groupN)_$(studentid1)_$(studentid2).zip”
(e.g. 1_109000001_109000002.zip) before uploading to e3. Other filenames and formats such as *.rar and *.7z are NOT accepted
○ report.pdf
● YourreportshouldbeinPDFformat.

● FeelfreetoaskonHackMDifyouneed. ○ Lab5討論區
● Wewillnotdebugforyou.
8. Reference
● RISC-Vcard

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