The goal of this LAB is to implement a 32-bit ALU (Arithmetic Logic Unit) with 32 1-bit ALUs. ALU is the basic computing component of a CPU. Its operations include AND, OR, addition, subtraction, etc. This series of LABs will help you understand the CPU architecture.

2. HW Requirement

• Please use Icarus Verilog and GTKWave as your HDL simulator.
• Please attach your name and student ID as comment at the top of each file.
• Please use the Testbench we provide you, and DO NOT modify it.
• The names of top module and IO ports must be named as follows:

Top module: alu.v

ALU starts to work when the signal rst_n is 1, and then catches the data from src1 and src2.

In order to have a good coding style, please obey the rules below:

One module is written in one file.

Module name and file name must be the same.

For example: The file alu.v only contains the module alu.

• Basic instruction set (60%)

• ZCV three flags: zero, carry out, and overflow (30%)

4. Bonus: Extra instruction set

Hint: Add a module named Compare in 1-bit ALU!