[SOLVED] Cda 4203l spring 2025 computer system design lab lab 5 – gcd design on fpga

Objective: To implement RTL Design of Greatest Common Denominator (GCD) of numbers.
Description: Design GCD architecture control/data paths for two 4-bit numbers (in your lecture
notes, we have already done this). It will output the binary value of the greatest common divisor of
those two 4-bit numbers.
1. Datapath
The datapath top-level module can be constructed by the instantiated individual
components. You can create these individual behavioral components (Register (DFF), notequal, less-than, subtractor, MUX, etc.) for each element in the datapath. Some examples
are given below.
Registers are the only clocked component in datapath (Example 1 below). Registers in
datapath should have enable signals coming from FSM module (to load X, Y, etc. to DFFs
in your datapath), and separate reset signals. All non-register components must be purely
combinational (Example 2 next page shows some but not all such components).
Example 1, one way to implement your registers:
Example 2, two of the components in the datapath but you need more:

2. Control path with FSM
The FSM top-level module, according to the current state, output signals that the datapath top-level
module use to perform arithmetic and to load or output from registers. The datapath top-level
module sends signals back to the FSM to use. The controller is run by the FSM, and it could run
on an opposite clock of the datapath (or you could run the clock for datapath with different speed,
or use any trick to make sure the “load” inputs are picked up by datapath registers correctly).
Develop a Moore Verilog code for FSM. FSM templates were given in Lab 4, use them here too.
In your FSM module, you can use parameters for the states, below is just one example you might
want to use in your Verilog (the states and their names below match those of the GCM example):
Points:
(50 pts.) Write structural Verilog for datapath and behavioral Verilog for controller (FSM). Use
the design we discussed in the class. The FSM Verilog code should strictly follow the FSM
template.
Your top_level entity (let us call it GCD_top) would instantiate the datapath and controlpath
modules. Connect the inputs/outputs of these two modules correctly. Is/Os of FSM are mostly
Os/Is of datapath and vice versa.
Deliverables (Only one .zip file per group) A zipped file (.zip) which includes these two items:
(a) Your group design files (Verilog Models and test benches). (b) A concise PDF group report
(that includes your Verilog code and simulation results) needs to be included in the submitted .zip
file.
Who submits? Only the group lead. Do not submit the same .zip file for each student.

PDF Report Organization to be included in your ZIP submission (A template is provided on
Canvas):
□ Cover sheet
□ Verilog Code, Test Bench, and Simulation Results (Waveforms)
□ Feedback: Hours spent, Exercise difficulty (Easy, Medium, Hard)
□ You need to submit your group report on Canvas in ZIP format (only one .zip file).