COMP2421 Computer Organization
2019/20 Semester 1
Lab 9 Logic Gate Design IV
In this lab, we will examine more sequential circuits: ➢ D Flip Flop
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➢ Master-Slave D Flip Flop
D Flip Flop
The disadvantage of SR Flip Flop is that there is an invalid state of the circuit if S and R are “1”. The D-Type circuit solve the problem.
[Exercise] Create the following circuit using Logisim and complete the table below:
Clock 00 01 10 11
COMP2421 Computer Organization 2019/20 Semester 1
Master-Slave D Flip Flop
[Exercise] Use “D Flip Flop” to create the following circuit in Logisim and check the result.
[Question] What is the purpose of this circuit?
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