[SOLVED] Hive Microsoft Word ECE2504_DP2-Spring2017

Microsoft Word ECE2504_DP2-Spring2017

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ECE2504IntroductiontoComputerEngineering(Spring2017)
DesignProject2:DesignandImplementationofanArithmeticLogicUnitontheDE0Nanoboard

Readtheentirespecificationbeforeyoubeginworkingonthisproject!

HonorCodeRequirements
Eachstudentmustcompletethisprojectandtheassociatedreportindividually.Donotdiscussanyaspectofyoursolution
orapproachwithanyoneexceptforyourinstructororaCELGTA.Considerallinformationthatyouderivefromyourdesign
processtobeproprietary.Amongotherthings,thisincludesthemannerinwhichyouimplementyouroperations,and
thenumberofchipsthatyouuse.CopyingorusinganyotherpersonsdesignisaviolationoftheVirginiaTechHonor
Code,andwillbeprosecutedassuch.YoumaydiscussgeneralfeaturesofQuartusandtheDE0Nanoboard.Directall
otherquestionstoyourGTAortoyourinstructor.

Objectives

Design,simulate,andimplementanArithmeticLogicUnitfromaspecification.
Writeaprojectreportdescribingthedesignprocessanditsresults.

Preparation
YoumusthaveaccesstoacomputerthatcanrunQuartus.YoumusthaveaDE0Nanoboard.

Readthisprojectspecificationinitsentirety.ConsulttheappropriatesectionsofChapter3andChapter8ofthetextbook.
Youshouldalsoconsult theDE0Nanoboardusersmanual,particularlyChapter3and6.This lab followsasimplified
versionofthestepsdescribedinChapter6oftheusersmanual.

ProjectDescription
Anarithmetic logicunit(ALU)isacombinationalcircuitthatperformsavarietyofcommonarithmetic, logic,andshift
operations.AnALUhasasetofcontrol inputs thatdeterminewhichof theoperationswillbecarriedoutonasetof
operands.Forthisproject,theALUwilltakeasinputtwo8bitoperands,AandB,andperformtheoperationonthose
operandsspecifiedbya4bitoperationcode(opcode).TheALUwillgeneratethe8bitresultoftheoperationaswellas
fourstatusbits.ThesetofoperationsthatyouarerequiredtoimplementisspecifiedinTable1.

Operationname Output
Statusbitsset

baseduponresult
Description

add A+B V,Z,C,N AddAandB

sub A+B+1 V,Z,C,N SubtractBfromA

dec A1 V,Z,C,N DecrementAby1

neg A+1 V,Z,C,N NegativeofA

or AB Z,N BitwiseORofAandB
nand (AB) Z,N BitwiseNANDofAandB
xnor (AB) Z,N BitwiseXNORofAandB
not A Z,N BitwisecomplementofA

mult8 B8 Z,N MultiplyBby8

rem16 Arem16 Z,N
RemainderofdivisionofAby16;NoteifAisnegative,

theresultwillbenegative

lsl
(logicalshiftleft)

B<<1 AllstatusbitsclearShiftBleftby1bit;thevacantbitpositionsarefilledinwith0csr(circularshiftright)B>>1 Allstatusbitsclear
ShiftBrightby1bit;thevacantbitpositionsarefilledin

withthebitsthatareshiftedoutofthesequence

Table1:RequiredALUoperations

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Thestatusbitsaredefinedtobethefollowing(seeTable1forwhichoperationsareaffected):

V:Overflow.Thisbitshouldbesetto1whenthereisanoverflowforanoperationassumingtheoperandsareintwos
complement;otherwisethebitshouldbe0.

Z:Zero.Thisbitshouldbesetto1whentheresultofanoperationisequaltodecimal0;otherwisethebitshouldbe
0.

C:Carryout.Thisbitshouldbesetto1whenthere isacarryoutfromthemostsignificantbitoftheresultofan
operation;otherwisethebitshouldbe0.

N:Negative.Thisbitshouldbesetto1whentheresultofanoperationisnegativeassumingtheresultisintwos
complement;otherwisethebitshouldbe0.

ThestatusbitsshouldbesetonlyfortheoperationsasshowninTable1.Forotheroperations,theyshouldbecleared.

Inthisprojectyouwilldesign,simulateandimplementan8bitALUthatperformstheoperationsspecifiedabove.Your
ALUwillbepartofalargersystemthatwillsupplyitwithinputsanddisplaytheoutputs.Thelargersystemisshownin
theschematicinFigure1.Yourresponsibilityistoimplementtheblocklabeledyour_ALU_mux.Therestofthesystem
hasbeenprovidedforyou.ThefilesfortheprojectareintheQuartusarchivedprojectpostedwiththisdescription.

ThesystemtakesasinputthefourDIPswitchesontheDE0Nanoboard(SW[3:0])andthetwopushbuttons(KEY[1:0]).
ThepushbuttonscontrolacounterthatgeneratesaddressesforasmallReadOnlyMemory(ROM).EachtimeKEY[1]is
pushedandreleased,thecounteradvancestothenextaddressintheROM,andanewsetofoperandsandopcodeis
appliedtotheinputsoftheyour_ALU_muxmodule.KEY[0]istheresetbutton;aftertheboardhasbeenprogrammed,it
shouldbepushedandreleasedbeforeperforminganyotheroperationstoputthedesignintoaknownstate.TheROM
containshas16words(addresses0through15),eachofwhichis20bitswide.Eachwordcontainstwo8bitoperandsand
a4bitopcode,arrangedasshowninFigure2.

19 16 15 8 7 0

Opcode OperandA OperandB

Table2.ContentsofeachROMaddress

ThecontentsoftheROMarecontainedinthefilecalledrom.txtintheQuartusproject.Eachlineofthetextfilehasthe
hexvalueforonememorylocation.Sinceeachwordis20bitswide,eachlineofthefilehasa5digithexnumber.For
example,address0intherom.txtprovidedwiththisprojectis4AA11,whichmeansthattheopcodeforaddress0is
4,operandAisAA16,andoperandBis1116.

Figure1.SchematicoffullsystemforDP2.Yourresponsibilityistoimplementtheyour_ALU_muxmodule.

Youwilldesignand
implementthismodule.

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Themoduleyour_ALU_muxshouldcontainyourALUaswellasa16to1muxthatcontrolsthevaluedisplayedonthe
LEDs.Theportdeclarationfortheyour_ALU_muxmoduleisasfollows:

module your_ALU_mux(your_out, operandA, operandB, opcode, switches, address);
input [7:0] operandA, operandB, address;
input [3:0] opcode, switches;
output [7:0] your_out;

Asshownontheschematic,theinputsoperandA,operandB,andopcodearesuppliedfromtheROMoutput,whilethe
address input is supplied by the counter. The switches input is connected to theDIP switches, SW[3:0]. The output,
your_out,isconnectedtotheLEDs,withLED[7]beingthemostsignificantbit.

TheDIPswitchescontrolthe16to1muxintheyour_ALU_muxmodule;themuxisusedtoselectwhichvalueisdisplayed
ontheLEDs.TheVerilogmodelprovidedfortheyour_ALU_muxmodulealreadyhasan8bitwide,16to1muxinstantiated
initwiththeDIPswitchesconnectedtotheselect lines.Youmustmodifytheinstantiationofthemuxtoprovidethe
outputsshowninTable3.Onlythebinaryvaluesfrom1000to1111arespecified;thevaluesfrom0000to0111areupto
you.Forexample,youmightusethemtodisplayvaluesfromtheALUotherthantheresultandstatusbitstohelpwith
debugging.YourreportshouldincludeatablesimilartoTable3thatlistshowtheLEDswereusedforeachcombination
oftheswitches,includingwhatyouassignedtoswitchvalues0000to0111.

YoumustincludethelastfourdigitsofyourstudentIDnumber(notPID,butstudentIDnumber)inBCDinthemodelusing
thelast_four_ID_digitsbusthatisdefinedintheyour_ALU_muxmodule.Forexample,ifthelastfourdigitsofyourID
numberwere1234,thenlast_four_ID_digitswouldbesetto16h1234or16b0001001000110100.AsshowninTable
3,theLEDsshouldthendisplay1216forSW[3:0]=1110and3416forSW[3:0]=1111.

SW[3:0] ValuedisplayedonLEDs

1000 Address

1001 Opcode,paddedwithleading0s:{4b0000,opcode}

1010 OperandA

1011 OperandB

1100 Result

1101 Statusbits,paddedwithleading0s:{4b0000,VZCN}

1110 LefttwodigitsofthelastfourdigitsofstudentID,inBCD

1111 RighttwodigitsofthelastfourdigitsofstudentID,inBCD

0XXX Availabletouseasyouseefit

Table3:DIPswitchselectlinesandvaluedisplayedonLEDs

Finally,theportdeclarationoftheALUisnotspecified.Ataminimum,theportsshouldincludethetwooperandsandthe
opcodeasinputs,andtheresultandstatusbitsasoutput.Youcanincludeotherinputsandoutputstohelpwithdebugging
thehardware.Aspartofyourdesignprocess,youwillhavetoassignspecific4bitopcodevaluesforeachoperation.Do
not simply assign an arbitrary opcode to a particular operation: Youwill find that groups of operations have similar
structuressuchthatacarefulchoiceoftheopcodeswillsimplifythe logicforcontrollingtheoperations.Yourproject
reportmustincludeatableshowingtheopcodevaluesthatyouchoseforeachoperation.

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Requirementsandconstraints
1. YouarepermittedtomodifyonlytheVerilogfileyour_ALU_mux.v,andtheROMcontentsfile,rom.txt.Youmustnot

modifyanyotherfileorschematicintheproject.Anyadditionalmodulesthatyoumightneedtocreatetoimplement
yourdesignshouldbeincludedintheyour_ALU_mux.vfile.

2. Youarenotpermittedtomodifytheportdeclarationoftheyour_ALU_muxmodule.
3. YoumustimplementyourdesignusingstructuralanddataflowVerilogconstructs(gateprimitives,assignstatements

withoperators).YouarenotpermittedtocreateanyschematicsortousebehavioralVerilogconstructs(e.g.,case
statements,forloops).NotethatifyouusedataflowVerilogitwillbemoredifficulttodetermineyourgatecountand
propagationdelay.

4. Yourdesignmustbecompletelycombinational.
5. YourdesignmustdisplaythelastfourdigitsofyourstudentIDnumberasshowninTable3.

Procedure
TheQuartusarchiveprojectfilepostedforthisproject includestheschematicandVerilog filesnecessarytobuildthe

system.Donotmodifyanyfilesexceptfortherom.txtfileandtheyour_ALU_mux.vfile.Inparticular,ifyouchange
thetoplevelschematicormodifythepinassignments,thereisachanceyoucoulddamageyourDE0Nanoboard.

WhiletheprovidedQuartusprojectdoesnotfullyimplementtheproject,itisfunctionalandcanbesynthesizedandthen
used toprogramFieldProgrammableGateArray (FPGA)on theDE0Nanoboardusing theprogramming instructions

providedbelow.Beforemodifyingtheyour_ALU_mux.vfile,youshouldprogramtheFPGAontheDE0Nanoboard
with the provided Quartus project to be sure you understand the programming procedure and the behavior of the
pushbuttonsandswitches.Youshouldconfirmthattheswitchsettingsbehaveasdescribedinthemodel.Asstatedabove,
theversionprovidedtoyoudoesnotcorrectlyimplementtheprojectspecification.

DevelopaVerilogmodeloftheALUbyitselfandtestitinsimulationtomakesureitbehavescorrectly.Youwillwantto
createanewprojectinQuartusjustforyourALU.(Theinstructionsforcreatinganewprojectandsimulatingamodel
havebeenprovidedinearlierassignments;pleaserefertothoseinstructionsifyouhaveanyquestionsaboutthosetasks.)
RatherthanbuildingthewholeALUandthensimulatingit,youshouldbuildandsimulatetheALUoneoperationatatime.
Dependinguponyourdesign,youmightcreatesmallerfunctionalblocksthatwillbeusedtoimplementtheALU;ifso,you
shouldsimulateeachofthoseblocksindividuallytomakesuretheybehavecorrectlybeforeyouconnectthemtogether
intolargerblocks.IncludesimulationresultsofyourALUforeachoperationformultipleoperandvaluesinyourreport.
Labeltheresultstoshowwhichoperationisbeingtested.Youshouldcarefullyconsiderwhichsetsofinputsareusedto
testyourALUsothatawidevarietyofcasesarecovered.

Once you are confident that yourALU isworking correctly, copy it into theyour_ALU_mux.v file in the provided
Quartusprojectandinstantiateit.Youcanthensimulatethewholesystem.Asamplesimulationinputfileisincludedwith

theproject,dp2_spring2017_input_waveform_example.vwf, to give youan ideahow to simulate the full
projectasshowninFigure2.ThecounterandROMintheschematicaresequentialcircuitsthatarepositiveedgetriggered,
sotheKEYandSWinputsshouldnotchangeonthepositiveedgeofclock.Furthermore,thecounteronlychangesthe
addressvaluewhenKEY[1]ispushedandthenreleased,soKEY[1]mustgofrom1to0andbackto1forthecounterto
advance.Finally,theKEYandSWvaluesshouldremainsteadyforseveralclockcyclesafteranychangeinvaluetomimic
therealhardware:theclockisrunningat50MHz,whichismuch(much!)fasterthanyoucanchangethepushbuttonsand
DIPswitches.Includesimulationresultsofthewholesysteminyourreport,showingthattheoutputbehavescorrectlyfor
severalcombinationsofswitchsettingsandALUoperations.

Afteryourmodelsimulatessatisfactorily,youmustcompileitandthenprogramtheDE0Nanoboardwithit.Pleaserefer
tosections6.8and6.9oftheDE0Nanousersmanualforfullinstructions.Briefly,tocompileyourdesign,doubleclick
CompileDesignintheTaskswindow,orselectProcessing>StartCompilationfromthetoolbar.Theprojectfilesprovided
toyouwillgenerate5warningsduringcompilation(9ifyouarerunningmultipleprocessors);thesecanbeignored.Ifyou
receivecriticalwarningsorerrors,however,youshouldcorrectthembeforecontinuing.Whenthecompilationcompletes
withnoerrors,itwillgenerateanSRAMObjectFile,.sof,whichyouwillusetoprogramtheFPGAontheDE0Nano

board.The*.soffilewillhavethesamenameastheproject,inthiscase,DP2_Spring2017.sof.

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Figure2.Sampleoutputsimulationfilefortestingthewholesystem.

Whentheprojectissuccessfullycompiled,youcanprogramtheDE0Nanoboard.Connecttheboardtoyourcomputer
using theUSBcableprovidedwith theboard.ThendoubleclickonProgramDevice (OpenProgrammer) in theTasks
window,orselectTools>Programmerfromthetoolbar.Theprogrammerwindowshouldopen,asshowninFigure3.The

DP2_Spring2017.soffileshouldbeshownasthefiletobedownloadedtotheboard.Ifitdoesnotappear,select
AddFileandthenselecttheDP2_Spring2017.soffilefromtheprojectdirectory.

Figure3.Programmerwindow.

Importantnote:Thefirsttimethatyouopentheprogrammerwindow,youmustclickHardwareSetup,andturnonthe
USBBlaster[USB0]optionundertheCurrentlyselectedhardwarepulldownmenuasshowninFigure4.Thenselect
closeandreturntotheprogrammerwindow.

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Figure4.ChoosingtheUSBBlasteroptionontheHardwareSetupwindow

Intheprogrammerwindow,clickontheStartbutton.Thestartbuttonwillgrayout,andtheLEDsontheDE0Nanoboard
willdim.Inafewseconds,theProgressindicatorontheprogrammerwindowshouldturngreenandsay100%(Successful).
Yourdesignhasnowbeendownloadedtotheboard.

Totestyourdesign,youshouldbeginbyresettingthecounterbypressingandreleasingtheKEY0pushbutton.Youcan
nowoperatethedesignbyusingtheDIPswitchestocontrolwhatisdisplayedontheLEDsandusingtheKEY1pushbutton
toadvancetothenextlocationintheROM.

OnceyouareconfidentthatyourdesignisworkingontheDE0Nanoboard,youshouldchangetherom.txtfilesothat
theoperationsareasshowninTable4(allvaluesareindecimal,butyoumustusehexadecimalintherom.txtfile),
whichwillbeusedtovalidateyourprojectintheCEL.

ROMaddress operation,operandA,operandB

0 sub,A=93,B=67

1 add,A=94,B=37

2 nand,A=74,B=122

3 xnor,A=41,B=42

4 not,A=23,B=123

5 mult8,A=62,B=13

6 or,A=67,B=89

7 neg,A=74,B=87

8 dec,A=58,B=114

9 rem16,A=53,B=87

A csr,A=85,B=117

B lsl,A=41,B=99

Table4.ROMcontentsofaddresses0Btobeusedforvalidation(allvaluesareindecimal)

UsingyourfinalALUdesign,determinethenumberof2inputgatesutilizedandthepropagationdelayoftheentireALU.
Includethisinformationinyourreport.Youmustincludeanexplanationofyourcalculationsandanyassumptions.

CircuitValidation
ThisprojectdoesnotrequireCELvalidation.Instead,youwillprovidethesourcefilesthatwillallowtheGTAtocompile
thesamefilesthatyouusedtoimplementyourALUontheDE0NanoBoard.Createanarchiveofyourworkbychoosing
Project>ArchiveProjectafteryoucompletetheimplementation.Whenyoucreatethearchive,itshouldappearinthe

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samefolderthatwascreatedwhenyouopenedtheoriginalarchive.UploadthearchivetoCanvas.Makecertainthatyou
uploadthecompletedarchivethatyoucreated,andnottheonethatwasprovidedtoyou.

ProjectReport
Afteryouhavevalidatedyourlogiccircuit,prepareandsubmitawrittenlabreportthatpresentsadetaileddiscussionof
theproject.Itshouldincludethedesignapproachyoufollowed,thefinaldesignyouimplement,thedesigndecisionsthat
youmadeandthealternativesyouconsidered,yoursimulationresults,yourobservations,andyourconclusions.Subdivide
yourreportintologicalsectionsandlabelthemasappropriate.Thelasttwopagesofyourreportmustbethevalidation
sheet.Besuretoincludealltherequiredelements.RefertotheAssignmentrubrictoseehowthisprojectwillbegraded.

SubmissionRequirements:

SubmitthefollowingfilesonCanvas.Donotputtheminazipfile!

1. YourArchivedProjectDP2_Spring2017_YourPID.QAR
2. YourcompletedVerilogfileyour_ALU_mux.v
3. Yourmodifiedmemoryfilerom.txt
4. Yourproject reportasapdfordoc.Remember the last twopages shouldbe thevalidationsheet.Remember to

completepage1ofthevalidationsheet!

Grading
Thedesignprojectwillbegradedona100pointbasis,asshownintheAssignmentrubric.