Computer Architecture
Course code: 0521292B 05. MIPS
Jianhua Li
College of Computer and Information
Hefei University of Technology
slides are adapted from CA course of wisc, princeton, mit, berkeley, etc.
The uses of the slides of this course are for educa/onal purposes only and should be
used only in conjunc/on with the textbook. Deriva/ves of the slides must
acknowledge the copyright no/ces of this and the originals.
1
CPU 53
Read register 1
Read register 2
Read data 1
Read data 2
Registers Write
register
Write data
Register numbers
5
5
Data
AL
Instruction
Add Sum Data
c. Adder
tion memory
b. Program counter
b.
PC
RegWrite
a. Registers
MemWrite
Add
a. Instruction memory b. Program counter MemRead c. Ad
Instruction address
Instruction memory
Instruction
Address Read
PC
Write data
data
Data memory
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
a. Data memory unit
b. Sign-extensi
Sum
der
16
Sign extend
n
n
A
U
A
o
(not practical) Magic memory and register file
Combinational read Synchronous write
Single-cycle, synchronous memory
(not practical) Magic memory and register file
Combinational read
output of the read data port is a combinational function of the register file contents and the corresponding read select port
Synchronous write
Single-cycle, synchronous memory
(not practical) Magicmemoryandregisterfile
Combinational read
output of the read data port is a combinational function of the register file contents and the corresponding read select port
Synchronous write
the selected register is updated on the positive edge
clock transition when write enable is asserted Cannot affect read output between clock edges
Single-cycle, synchronous memory
(not practical)
Magic memory and register file
Combinational read
output of the read data port is a combinational function of the register file contents and the corresponding read select port
Synchronous write
the selected register is updated on the positive edge clock transition when write enable is asserted
Cannot affect read output between clock edges
Single-cycle, synchronous memory
Contrast this with memory that tells when the data is ready i.e., Ready bit: indicating the read or write is done
MIPS
5 generic steps
Instruction fetch (IF)
Instruction decode and register operand fetch (ID/RF) Execute/Evaluate memory address (EX/AG)
Memory operand fetch (MEM)
Store/writeback result (WB)
WB
ALU
Address Instruction
Instruction memory
IF
PC
Address
Data memory
Data
MEM
ID/RF
Data
Register # Registers
Register #
Register #
EX/AG
MIPS
Instruction [25 0]
Shift
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
26 left2 28
PC+4 [31 28]
Read address
Instruction memory
Instruction [31 0]
Read register 1
Read register 2
Read data 1
Instruction [20 16]
0 M
u x
1
Write Registers Read register data 2
Write data
Address
Read data
Instruction [15 11]
1
M u x
0
Write data
Data memory
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
ALU control
ALU operation
0
M u x
1
bcZoenrdo ALU ALU
result
JAL, JR, JALR omitted
R-Type ALU Instructions
Assembly (e.g., register-register signed addition) ADD rdreg rsreg rtreg
Machine encoding
6-bit 5-bit 5-bit 5-bit 5-bit
Semantics
if MEM[PC] == ADD rd rs rt
GPR[rd] GPR[rs] + GPR[rt]
PC PC + 4
R-type
0
rs
rt
rd
0
ADD
6-bit
PC
Read address
Instruction memory
Instruction
20:16
Read register 1
Read register 2
Read data 1
Read data 2
15:11
Registers Write
register
Write data
IF
ID
EX
MEM
WB
if MEM[PC] == ADD rd rs rt
GPR[rd] GPR[rs] + GPR[rt]
PC PC + 4
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
ALU Datapath
4
Add
ALU operation
Zero
ALU ALU result
25:21
3
Instruction
RegWrite
1
Combinational state update logic
I-Type ALU Instructions
Assembly (e.g., register-immediate signed additions)
ADDI rtreg rsreg immediate16
Machineencoding
6-bit 5-bit 5-bit 16-bit
Semantics
if MEM[PC] == ADDI rt rs immediate
I-type
ADDI
rs
rt
immediate
GPR[rt] GPR[rs] + sign-extend (immediate) PC PC + 4
PC
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
RegWrite
1
16 Sign 32 extend
IF
ID
EX
MEM
WB
if MEM[PC] == ADDI rt rs immediate
GPR[rt] GPR[rs] + sign-extend (immediate) PC PC + 4
Datapath for R and I-Type ALU Insts.
4
Add
ALU operation
Zero
ALU ALU result
3
25:21 20:16
Mem
Data memo
Mem
Instruction
15:11
Address
Write data
Combinational state update logic
PC
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
RegWrite
1
16 Sign 32 extend
IF
ID
EX
MEM
WB
if MEM[PC] == ADDI rt rs immediate
GPR[rt] GPR[rs] + sign-extend (immediate) PC PC + 4
Datapath for R and I-Type ALU Insts.
4
Add
ALU operation
Zero
ALU ALU result
3
25:21 20:16
Mem
Data memo
Mem
Instruction
15:11
Address
Write data
?
Combinational state update logic
PC
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
RegWrite
1
ALUSrc
16 Sign 32 isItype extend
IF
ID
EX
MEM
WB
if MEM[PC] == ADDI rt rs immediate
GPR[rt] GPR[rs] + sign-extend (immediate) PC PC + 4
Datapath for R and I-Type ALU Insts.
4
Add
ALU operation
Zero
ALU ALU result
3
25:21 20:16
Mem
Data memo
Mem
Instruction
15:11
RegDest
isItype
?
Address
Write data
Combinational state update logic
Load Instructions
Assembly (e.g., load 4-byte word) LW rtreg offset16 (basereg)
Machineencoding
6-bit 5-bit 5-bit 16-bit
Semantics
if MEM[PC]==LW rt offset16 (base)
EA = sign-extend(offset) + GPR[base] GPR[rt] MEM[ translate(EA) ]
PC PC + 4
I-type
LW
base
rt
offset
Add
Instruction
RegDest
isItype
LW add
0
MemWrite
4
PC
3
ALU operation
Zero
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
ALU ALU result
ALUSrc
32 isItype
16
RegWrite
1
Addre
Write data
if MEM[PC]==LW rt offset16 (base)
EA = sign-extend(offset) + GPR[base] GPR[rt] MEM[ translate(EA) ]
PC PC + 4
16
Sign extend
MemRead
MemRead
a. Data m1emory unit
IF
ID
MemWrite
Address
ss
Data data Data memory
memory
Write
b. S
EX
Combinational state update logic
Read data
Read data
MEM
WB
i
Add
Instruction
RegDest
isItype
LW ?
add
ALU operation
Zero
0
MemWrite
4
PC
3
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
ALU ALU result
ALUSrc
32 isItype
16
RegWrite
1
Addre
Write data
if MEM[PC]==LW rt offset16 (base)
EA = sign-extend(offset) + GPR[base] GPR[rt] MEM[ translate(EA) ]
PC PC + 4
16
Sign extend
MemRead
MemRead
a. Data m1emory unit
IF
ID
MemWrite
Address
ss
Data data Data memory
memory
Write
b. S
EX
Combinational state update logic
Read data
Read data
MEM
WB
i
Store Instructions
Assembly (e.g., store 4-byte word) SW rtreg offset16 (basereg)
Machine encoding
6-bit 5-bit 5-bit 16-bit
Semantics
if MEM[PC]==SW rt offset16 (base) EA = sign-extend(offset) + GPR[base]
MEM[ translate(EA) ] GPR[rt] PC PC + 4
I-type
SW
base
rt
offset
Add
Instruction
RegDest
isItype
SW add
1
MemWrite
4
PC
3
ALU operation
Zero
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
ALU ALU result
ALUSrc
32 isItype
16
RegWrite
0
Addre
Write data
if MEM[PC]==SW rt offset16 (base)
EA = sign-extend(offset) + GPR[base] MEM[ translate(EA) ] GPR[rt]
PC PC + 4
16
Sign extend
MemRead
MemRead
a. Data m0emory unit
IF
ID
MemWrite
Address
ss
Data data Data memory
memory
Write
EX
Read data
Read data
b. S
Combinational state update logic
MEM
WB
i
Add
Instruction
RegDest
isItype
SW ?
add
ALU operation
Zero
1
MemWrite
4
PC
3
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
ALU ALU result
ALUSrc
32 isItype
16
RegWrite
0
Addre
Write data
if MEM[PC]==SW rt offset16 (base)
EA = sign-extend(offset) + GPR[base] MEM[ translate(EA) ] GPR[rt]
PC PC + 4
16
Sign extend
MemRead
MemRead
a. Data m0emory unit
IF
ID
MemWrite
Address
ss
Data data Data memory
memory
Write
EX
Read data
Read data
b. S
Combinational state update logic
MEM
WB
i
Load-Store Add
add
ALU operation
Zero
ALU ALU result
4
nstruction
RegDest
isItype
3
isStore
MemWrite
PC
Read address
Instruction I
Instruction memory
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
RegWrite
!isStore
Sign 32 extend
ALUSrc
isItype
16
MemRead
isLoad
Address
Read data
Write data
Data memory
PC
Read address
Instruction I
Instruction memory
4
Add
Read register 1
Read register 2
Read data 1
ALU operation
Zero
ALU ALU result
isStore
MemWrite
3
nstruction
RegDest
isItype
Write Registers register
Write data
Read data 2
RegWrite
!isStore
Sign 32 extend
ALUSrc
isItype
Address
Read data
Write data
Data memory
16
MemRead
isLoad
MemtoReg
isLoad
Assembly
J immediate26
Machine encoding 6-bit 26-bit
Semantics
if MEM[PC]==J immediate26
target = { PC[31:28], immediate26, 2b00 } PC target
J-type
J
immediate
4
Add
PC
ALU operation
Zero
ALU ALU result
3
MemWrite
Read address
Instruction I
Instruction memory
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
RegWrite
16 32 ALUSrc
Sign extend
MemRead
Address
Read data
Write data
Data memory
nstruction
if MEM[PC]==J immediate26
PC = { PC[31:28], immediate26, 2b00 }
4
3 XALU operation Zero
ALU ALU result
Add
0
MemWrite
PC
Read address
Instruction I
Instruction memory
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
RegWrite
016 32 Sign
extend
ALUSrc
Address
Read data
Write data
Data memory
X
MemRead
0
nstruction
if MEM[PC]==J immediate26
PC = { PC[31:28], immediate26, 2b00 }
isJ
PCSrc
Add
4
3 XALU operation Zero
ALU ALU result
0
MemWrite
PC
Read address
Instruction I
Instruction memory
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
Address
Read data
RegWrite
016 32 Sign
extend
ALUSrc
Write data
Data memory
X
MemRead
0
nstruction
concat
if MEM[PC]==J immediate26
PC = { PC[31:28], immediate26, 2b00 }
isJ
PCSrc
Add
4
3 XALU operation Zero
ALU ALU result
0
MemWrite
PC
Read address
Instruction I
Instruction memory
Read register 1
Read register 2
Read data 1
Write Registers register
Write data
Read data 2
Address
Read data
RegWrite
016 32 Sign
extend
ALUSrc
Write data
Data memory
X
MemRead
0
nstruction
concat
What about JR, JAL, JALR?
if MEM[PC]==J immediate26
PC = { PC[31:28], immediate26, 2b00 }
Assembly (e.g., branch if equal) BEQ rsreg rtreg immediate16
Machine encoding
6-bit 5-bit 5-bit 16-bit
I-type
BEQ
rs
rt
immediate
Semantics (assuming no branch delay slot)
if MEM[PC]==BEQ rs rt immediate16
target = PC + 4 + sign-extend(immediate) x 4 if GPR[rs]==GPR[rt] then PC target
else PC PC + 4
Conditional Branch Datapath (for you to finish)
PCSrc
Add Sum
sub
Branch target
4
Add
watch out
PC + 4 from instruction datapath
Shift left 2
PC
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Read data 2
Registers Write
register
Write data
ALU operation
Instruction
3
ALU bZceonrod
To branch control logic
RegWrite
16
0
Sign 32 extend
Conditional Branch Datapath (for you to finish)
PCSrc
Add Sum
sub
Branch target
4
Add
watch out
PC + 4 from instruction datapath
Shift left 2
PC
Read address
Instruction memory
Instruction
Read register 1
Read register 2
Read data 1
Read data 2
Registers Write
register
Write data
ALU operation
Instruction
3
ALU bZceonrod
concat
To branch control logic
RegWrite
16
0
Sign 32 extend
Putting It All Together
Instruction [25 0]
Shift
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
26 left2 28
PC+4 [31 28]
Read address
Instruction memory
Instruction [31 0]
Read register 1
Read register 2
Read data 1
Instruction [20 16]
0 M
u x
1
Write Registers Read register data 2
Write data
Address
Read data
Instruction [15 11]
1
M u x
0
Write data
Data memory
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
ALU control
ALU operation
0
M u x
1
bcoZnedro ALU ALU
result
JAL, JR, JALR omitted
AscombinationalfunctionofInst=MEM[PC]
31 26 21 16 11 6 0
R-type
I-type J-type
0
rs
rt
rd
shamt
funct
6-bit 5-bit 5-bit
31 26 21 16
5-bit 16-bit
5-bit
6-bit
opcode
rs
rt
immediate
6-bit
31 26
6-bit
5-bit 26-bit
5-bit
0
0
opcode
immediate
Consider
All R-type and I-type ALU instructions LW and SW
BEQ, BNE, BLEZ, BGTZ
J, JR, JAL, JALR
When De-asserted
When asserted
Equation
RegDest
GPR write select according to rt, i.e., inst[20:16]
GPR write select according to rd, i.e., inst[15:11]
opcode==0
ALUSrc
2nd ALU input from 2nd GPR read port
2nd ALU input from sign- extended 16-bit immediate
(opcode!=0) && (opcode!=BEQ) && (opcode!=BNE)
MemtoReg
Steer ALU result to GPR write port
steer memory load to GPR wr. port
opcode==LW
RegWrite
GPR write disabled
GPR write enabled
(opcode!=SW) && (opcode!=Bxx) && (opcode!=J) && (opcode!=JR))
JAL and JALR require additional RegDest and MemtoReg options
When De-asserted
When asserted
Equation
MemRead
Memory read disabled
Memory read port return load value
opcode==LW
MemWrite
Memory write disabled
Memory write enabled
opcode==SW
PCSrc1
According to PCSrc2
next PC is based on 26- bit immediate jump target
(opcode==J) || (opcode==JAL)
PCSrc2
next PC = PC + 4
next PC is based on 16- bit immediate branch target
(opcode==Bxx) && bcond is satisfied
JR and JALR require additional PCSrc options
ALU Control
0 select operation according to funct
ALUi selection operation according to opcode LW select addition
SW select addition
Bxx select bcond generation function
__ dont care
Example ALU operations
ADD, SUB, AND, OR, XOR, NOR, etc.
bcond on equal, not equal, LE zero, GT zero, etc.
case opcode
R-Type ALU
Instruction [25 0]
Shift
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
26 left2 28
PC+4 [31 28]
Read address
Instruction memory
Instruction [31 0]
Read register 1
Read register 2
Read data 1
Instruction [20 16]
0 M
u x
1
Write Registers Read register data 2
Write data
Address
Read data
Instruction [15 11]
1
M u x
0
Write data
Data memory
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
ALU control
ALU operation
0
M u x
1
bZceonrod
ALU ALU result
Instruction [25 0]
Shift
R-Type ALU
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Read register 1
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
1
0
1
M
u Mu
PC
Read data 1
26 left2 28
PC+4 [31 28]
Read address
Instruction memory
Instruction [31 0]
Instruction [20 16]
Instruction [15 11]
0 M
u x
1
Address
Read data
Write data
Data memory
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
functALU operation ALU
c
0
ont
rol
Read
register 2
Write Registers Read 0
bZceonrod ALU ALU
result
register data 2
x x
Write
data 1 0
Instruction [25 0]
Shift
I-Type ALU
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Read register 1
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
1
0
1
u Mu
PC
Read data 1
Read address
Instruction memory
Instruction [31 0]
26 left2 28
PC+4 [31 28]
Instruction [20 16]
0 M
u x
1
Instruction [15 11]
Address
Read data
Write data
Data memory
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
opco ALU operation ALUde
co
0
ntr
ol
Read
register 2
Write Registers Read 0 ALU ALU
register data 2
bcZoenrod M result
x x
Write
data 1 0
Instruction [25 0]
Shift
LW
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite 1
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
Read register 1
Read data 1
0
1
u Mu
26 left2 28
PC+4 [31 28]
Read address
Instruction memory
Instruction [31 0]
Instruction [20 16]
Instruction [15 11]
0 M
u x
1
Address
Read data
Write data
Data memory
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
Add ALU operation ALU
co
1
ntro
l
Read
register 2
Write Registers Read 0 ALU ALU
register data 2
bcoZnedro M result
x x
Write
data 1 0
Instruction [25 0]
Shift
SW
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite 0
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
Read register 1
Read data 1
1
Read address
Instruction memory
Instruction [31 0]
26 left2 28
PC+4 [31 28]
Instruction [20 16]
0
Instruction[1511] XMux 1
Instruction [15 0]
Address
Read data
Write data
Data memory
16 Sign 32 extend
Instruction [5 0]
Add ALU operation ALU
co
0
ntro
l
Read
register 2
Write Registers Read 0 ALU ALU
register
Write data
data 2
bcoZnedro M result
u
x 1
1
XMux 0
Branch (Not Taken)
Instruction [25 0]
Shift
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite 0
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
Read register 1
Read data 1
0
Read address
Instruction memory
Instruction [31 0]
26 left2 28
PC+4 [31 28]
Instruction [20 16]
0 M
Instruction [15 11] Xux 1
Instruction [15 0]
Address
Read data
Write data
Data memory
16 Sign 32 extend
Instruction [5 0]
bcon ALU operation ALUd
co
0
ntro
l
Read
register 2
Write Registers Read 0 ALU ALU
register
Write data
data 2
bcoZnedro M result
u
x 1
1
XMux 0
Branch (Taken)
Instruction [25 0]
Shift
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite 0
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
Read register 1
Read data 1
0
Read address
Instruction memory
Instruction [31 0]
26 left2 28
PC+4 [31 28]
Instruction [20 16]
0 M
Instruction [15 11] Xux 1
Instruction [15 0]
Address
Read data
Write data
Data memory
16 Sign 32 extend
Instruction [5 0]
bcon ALU operation ALUd
co
0
ntro
l
Read
register 2
Write Registers Read 0 ALU ALU
register
Write data
data 2
bcoZnedro M result
u
x 1
1
XMux 0
Branch (Taken)
Some control signals are dependent on the processing of data
Instruction [25 0]
Shift
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst Shift Jump left 2
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite 0
Read register 1
Read
register 2
Write Registers Read 0
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
Read data 1
0
Read address
Instruction memory
Instruction [31 0]
26 left2 28
PC+4 [31 28]
Instruction [20 16]
0 M
Instruction [15 11] Xux 1
Instruction [15 0]
Address
Read data
Write data
Data memory
16 Sign 32 extend
Instruction [5 0]
bcon ALU operation ALUd
co
0
ntro
l
register
Write data
data 2 M
u
x 1
bcoZnedro
ALU ALU result
1
XMux 0
Instruction [25 0]
Shift
Jump
Jump address [31 0]
PCSrc1=Jump
01 MM Xux ux
10
PCSrc2=Br Taken
Add ALU result
Add 4
RegDst Shift
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite 0
Read register 1
left 2
Instruction [31 26]
Instruction [25 21]
Control
PC
Read data 1
0
Read address
Instruction memory
Instruction [31 0]
26 left2 28
PC+4 [31 28]
Instruction [20 16]
0 M
Instruction[1511] Xux 1
Instruction [15 0]
Address
Read data
Write data
Data memory
16 Sign 32 extend
Instruction [5 0]
XALU control
ALU operation
0
Read
register 2
Write Registers Read 0
bcoZnedro
ALU ALU result
register
Write data
data 2
M u x
1 u
X
XM x
1
0
What is in That Control Box?
Combinational LogicHardwired Control Idea: Control signals generated combinationally
based on instruction
Necessary in a single-cycle microarchitecture
Sequential Logic Sequential/Microprogrammed Control
What is in That Control Box?
Combinational LogicHardwired Control Idea: Control signals generated combinationally
based on instruction
Necessary in a single-cycle microarchitecture
Sequential Logic Sequential/Microprogrammed Control
Idea: A memory structure contains the control signals associated with an instruction
Control Store
MIPS
A Single-Cycle Microarchitecture: Analysis
Every instruction takes 1 cycle to execute CPI (Cycles per instruction) is strictly 1
A Single-Cycle Microarchitecture: Analysis
Every instruction takes 1 cycle to execute CPI (Cycles per instruction) is strictly 1
How long each instruction takes is determined by how long the slowest instruction takes to execute
Even though many instructions do not need that long to execute
A Single-Cycle Microarchitecture: Analysis
Every instruction takes 1 cycle to execute CPI (Cycles per instruction) is strictly 1
How long each instruction takes is determined by how long the slowest instruction takes to execute
Even though many instructions do not need that long to execute
Clock cycle time of the microarchitecture is determined by how long it takes to complete the slowest instruction
Critical path of the design is determined by the processing time of the slowest instruction
What is the Slowest Instruction to Process?
Lets go back to the basics
All five phases of the instruction processing cycle
take a single machine clock cycle to complete
Instruction fetch (IF)
Instruction decode and register operand fetch (ID/RF) Execute/Evaluate memory address (EX/AG)
Memory operand fetch (MEM)
Store/writeback result (WB)
What is the Slowest Instruction to Process?
Lets go back to the basics
All five phases of the instruction processing cycle
take a single machine clock cycle to complete
Instruction fetch (IF)
Instruction decode and register operand fetch (ID/RF) Execute/Evaluate memory address (EX/AG)
Memory operand fetch (MEM)
Store/writeback result (WB)
Do each of the above phases take the same time (latency) for all instructions?
Assume
memory units (read or write): 200 ps
ALU and adders: 100 ps
register file (read or write): 50 ps other combinational logic: 0 ps
steps
IF
ID
EX
MEM
WB
Delay
resources
mem
RF
ALU
mem
RF
R-type
200
50
100
50
400
I-type
200
50
100
50
400
LW
200
50
100
200
50
600
SW
200
50
100
200
550
Branch
200
50
100
350
Jump
200
200
Instruction [25 0]
Shift
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
PC
26 left2 28
PC+4 [31 28]
Read address
Instruction memory
Instruction [31 0]
Read register 1
Read register 2
Read data 1
Instruction [20 16]
0 M
u x
1
Write Registers Read register data 2
Write data
Address
Read data
Instruction [15 11]
1
M u x
0
Write data
Data memory
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
ALU control
ALU operation
0
M u x
1
bcoZnedro
ALU ALU result
26 left2 28
PC+4 [31 28]
100ps
PC
Read address
Instruction memory
200ps
Read register 1
Read register 2
Read data 1
Instruction [20 16]
0 M
u x
1
Write Registers Read register data 2
250ps
0
Instruction [31 0]
Address
350ps
Write data
Read data
Write 400ps data
M u x
1
bcoZnedro
ALU ALU result
Data memory
1
M u x
0
Instruction [15 11]
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
ALU control
ALU operation
R-Type and I-Type ALU
Instruction [25 0]
100ps
Shift
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
PCSrc2=Br Taken
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
Instruction [31 26]
Instruction [25 21]
Control
100ps
26 left2 28
PC+4 [31 28]
100ps
PC
Read address
200ps
Read register 1
Read register 2
Read data 1
Instruction [20 16]
Write Registers Read register data 2
250ps
Instruction [31 0]
0
M u x
1
bcZoenrod
ALU ALU result
Address
350ps
Write data
Read 550ps M
data 1
Instruction memory
Instruction [15 11]
Instruction [15 0]
0 M
u x
1
Write
600ps
Data memory
u
data
16 Sign 32 extend
Instruction [5 0]
x 0
ALU control
ALU operation
Instruction [25 0]
Shift
LW
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
PCSrc2=Br Taken
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
Instruction [31 26]
Instruction [25 21]
Control
[Based on original figure from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
26 left2 28
PC+4 [31 28]
100ps
100ps
PC
Read address
200ps
Read register 1
Read register 2
Read data 1
0
M u x
1
bcZoenrod
ALU ALU result
1
M u x
0
Instruction memory
Instruction [31 0]
Instruction [20 16]
250ps
Write Registers Read register data 2
Write data
Instruction [15 11]
0 M
u x
1
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
Address
Read data
memory 350ps 5 Data
Writ data
50ps
e
ALU control
ALU operation
Instruction [25 0]
Shift
SW
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
PCSrc2=Br Taken
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
Instruction [31 26]
Instruction [25 21]
Control
100ps
26 left2 28
PC+4 [31 28]
350ps
350ps
PC
Read address
200ps
Instruction [31 0]
Instruction [20 16]
Read register 1
Read register 2
Read data 1
250ps
Write Registers Read register data 2
Write data
Instruction memory
Instruction [15 11]
0 M
u x
1
0
M u x
1
bcZoenrod
ALU ALU result
Address
Read data
Write data
Data memory
1
M u x
0
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
ALU control
ALU operation
Instruction [25 0]
Branch Taken
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
Shift
200ps
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
AddALU 1 0 result
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
26 left2 28
100ps
PC+4 [31 28]
200ps
PC
Read address
200ps
Read register 1
Read register 2
Read data 1
Instruction [20 16]
Instruction [31 0]
0 M
u x
1
Write Registers Read register data 2
Write data
Instruction memory
Address
Read data
Write data
Data memory
1
M u x
0
Instruction [15 11]
Instruction [15 0]
16 Sign 32 extend
Instruction [5 0]
ALU control
ALU operation
Instruction [25 0]
Shift
Jump
Jump address [31 0]
PCSrc1=Jump
01
MM uu xx
AddALU 1 0 result
Add 4
RegDst
Jump
Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite
Shift left 2
PCSrc2=Br Taken
Instruction [31 26]
Instruction [25 21]
Control
0
M u x
1
bcZoenrod
ALU ALU result
Next Topic Pipelining & Hazards
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