slides are adapted from CA course of wisc, princeton, mit, berkeley, etc.
The uses of the slides of this course are for educa/onal purposes only and should be 1 used only in conjunc/on with the textbook. Deriva/ves of the slides must
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Instruction Set Architecture (ISA)
The contract between software and hardware
Functional definition of operations, modes, and storage locations
supported by hardware
Precise description of how software can invoke and access them
Instruction Set Architecture (ISA)
The contract between software and hardware
Functional definition of operations, modes, and storage locations
supported by hardware
Precise description of how software can invoke and access them
Strictly speaking, ISA is the architecture
Informally, architecture is also used to talk about the big picture of implementation
Better to call this microarchitecture
M
icro
ISA
No
architecture ()
specifies what hardware
guarantees regarding
How operations are implemented
Which operations are
Which operations take more power
doe
fast and whic
s,
not how it does
h are
and which
slow
take les
it
s
M
icro
ISA
No
architecture ()
specifies what hardware
guarantees regarding
How operations are implemented
Which operations are
Which operations take more power
These issues are determined by the
doe
fast and whic
Microarchitecture = how hardware implements architecture All Pentiums implement the x86 architecture
s,
not how it does
h are
and which
microar
slow
chitecture
take les
it
s
ISA
1.
2.
3.
4.
5. 6.
Th
e Von N
Operations
Operand model
Where
Datatypes Control
eu
mann model
Implicit structure of all mo
Format
Length and encoding
are operands stored and h
and operations
dern ISAs
ow do addres
s them?
ISA
1.
2.
3.
4.
5. 6.
Th
e Von N
Operations
Operand model
Where
Datatypes Control
eu
mann model
Implicit structure of all mo
Format
Length and encoding
are operands stored and h
and operations
: MIP
S ISA
:
dern ISAs
MIPS
ow do addres
CPU
s them?
1. Von Neu
Fetch PC
Execute
Write Output
mann
Model
Implicit model of all
Key: program counter (PC
m
odern ISAs
Defines total order
of
Order and named storage define computation
Value flows from insn X to Y via storage A iff
X names A as output, Y
And Y a
fter X
in
total order
Processor logically executes loop at left Instruction execution assumed atomic
Instruction X finishe
s before
)
Decode
dynamic instructions
Read Inputs
Next
PC is
PC++ unless
insn says otherwise
Next PC
names A a
insn
X+1 starts
s input
2. Instructio
Leng
1.
2.
3.
th
Varia
Compro
()
Fixed length
32 or 64 bits
+
Sim
Code densit
ble le
Exa
n Format
ple implem
ngth
Complex implementation + Code density
y
mise: two lengths
mple: MIPS16
entation: com
pute next PC
using only
PC
2. Instructio
Leng
1.
2.
3.
En
th
Fixed length
32 or 64 bits
+
Varia
Sim
ble le
Exa
n Format
ple implem
Code densit
ngth
Complex implementation + Code density
Compro
y
mise: two lengths
mple: MIPS16
entation: com
coding ()
A few simple encodings simplify decoder implementation
Complex encoding
can improve code
pute next PC
density
using only
PC
M
L
IP
S
ength
Format
32-bits
MIPS16: 16-bit
()
variants of common instructio
ns
for density
M
L
IP
S
ength
Encodin
R-type
Format
32-bits
MIPS16: 16-bit
g
3 formats, simple encoding
Q: how many opera
Op(6)
()
variants of common instructio
Rs(5)
tion types can be e
Rt(5)
Rd(5)
Sh(
ns
Func(6)
for density
ncoded in 6-bit opcode?
5)
I-typ
J-type
e
Op(6)
Op(6)
Rs(5)
Rt(5)
Target(26)
Im
med(16)
R Format () 655556
e.g., add $1, $2, $3
000000 00010 00011 00001 00000 100000 alu-rr 2 3 1 zero add/signed
opcode
rs
rt
rd
shamt
funct
I Format ()
All loads and stores use I-format Assembly: lw $1, 100($2)
Machine:
100011 00010 00001 0000000001100100 lw 2 1 100 (in binary)
opcode rs rt addr/immediate
6
5
5
16
I Format ()
ALU ops with immediates
addi $1, $2, 100
001000 00010 00001 0000000001100100
Conditional branches
beq $1, $2, 7
000100 00001 00010 0000 0000 0000 0111
PC = PC + (0000 0111 << 2) // word offsetJ Format ()Direct Jump:opcode addr6 26J Format ()Direct Jump:opcode addr6 26 Jump to:New PC = 4 MSB of PC || addr || 00 4+26+2 = 32 bits for jump target3. OperationsOperationtypeencoded in instructionopcode3. OperaOperation Integer a FParithmetic:tionstypeMany types of operatiencodrithmetic: add Integer logical: and, or, xor, ed in instons, sub, mul,add, sub, mul, div,ructiondiv, mod/remsqrtnot, sll, srl, sraopcod(siegned/unsigned) 3. OperaOperation Integer a FParithmetic:tionstypeMany types of operatiencodrithmetic: add Integer logical: and, or, xor, What other operations mighted in instons, sub, mul,add, sub, mul, div,ructiondiv, mod/remsqrtnot, sll, srl, srabe useful?opcod(siegned/unsigned)3. OperaOperation Integer a FParithmetic:tionstypeMany types of operatiencodrithmetic: add Integer logical: and, or, xor,ed in instons, sub, mul,add, sub, mul, d What other operations might be useful? More operation types == better ISA?iv,ructiondiv, mod/remsqrtnot, sll, srl, sraopcod(siegned/unsigned)3. OperaOperation FPDEC VAXarithmetic:tionstypeMany types of operati Integer a Integer logical: and, or, xor, E.g., instructioencodrithmetic: added in instons, sub, mul,add, sub, mul, d What other operations might be useful? More operation types == better ISA?computer had LOTS of on for polynomialiv,evructiondiv, mod/remsqrtnot, sll, srl, sraaluatiperaonopcod(siegned/untion types(no joke!)signed)3. OperaOperation FParithmetic:tionstypeMany types of operati Integer a Integer logical: and, or, xor, E.g., instructio Butencodrithmetic: added in instons, sub, mul,add, sub, mul, d What other operations might be useful? More operation types == better ISA?DEC VAXcomputer had LOTS of on for polynomialmany of them were rarely/neveriv,evructiondiv, mod/remsqrtnot, sll, srl, sraaluatiusperaonedopcod(siegned/untion types(no joke!)signed)4. Operand Model ()Ifyouregoing toadd, you Two source operands, one destination op Question #1: Where can operands coQuestion #2: And how areneed at leastthey specified?3operandserandme from? 4. Operand Model ()IfyoureQuestion #2: ARunning egoing toDiscuss: Memory-OnlOptional: Accumulator & Staadd, you Two source operands, one destination op Question #1: Where can operands cond how arexample: A = B + C Several options for answering both questionsy & Reneed at leastthey specified?gistersck3operandserandme from? Operand ModelI:MemoryOnlyMemoryonlyadd A,B,Cmem[A] =mem[B]+ mem[C] MEM OperandAccumuloadadd Cstore ABlatorMo:del II:implicit singleAccumulatorACC-element= mem[B]ACC = ACC + mem[C] mem[A] = ACCstackACC MEM OperandStackpushpushaddpop ABCMo: top of stackdelIII: Stack(TOS)stack[Tstack[T stack[Tmem[A] =isimplicit in instructionOS++] = mem[B]OS++] = mem[C]OS++] = stack[–TOS] + stack[–TOS]stack[–TOS]sTOSMEMOLperandGeneralloadadd R1, Cstore R1,Aoad-store :load R1,B load R2,Cadd R1,R1,R2store R1,AModelIV: Registers-purpose registers : multipleR1,BGPR and only loaR1 = mem[B]R1 = R1 + mem[C] mem[A] = R1R1 = mem[B] R2 = mem[C]R1 = R1 + R2mem[A]=ds/storR1explicit accumulatores access memorysMEMOperandMetric I:Mostatic codedel: Pros Number of instructions needed to Evaluation: register < load-storesizeandConsrepresent program, size < memory onlyofeachOperandMetric I:Model: Prosstatic code Number of instructions needed to Evaluation: register < load-storeMetric II: data mem Number of bytes Evaluation:load-storesizeory trafficmoved to and from> register
and
Cons
represent program, size < memory onlymemory> memo
ry only
of
each
O
perand
Metric I:
Metric II: data mem
Number of bytes
Wa
Mo
static code
nt low latency to
Evaluation:
del: Pros
Number of instructions needed to Evaluation: register < load-storeload-storesizeory trafficmoved to and from Evaluation: load-store < register < memoMetric III: instruction latencyandexecute instructions> register
Cons
represent program, size < memory onlymemory> memory only
ry only
of
each
O
perand
Metric I:
Number of bytes
Evaluation:
:
Mo
static code
del: Pros
Number of instructions needed to Evaluation: register < load-storeMetric II: data memload-storemost current ISAs aresizeory trafficmoved to and from Evaluation: load-store < register < memo Metric III: instruction latency Want low latency toandexecute instructions< register < memoload-StoreConsrepresent program, size < memory onlymemoryry onlyry onlyofeachMIPMIPSS 32 32-bit HI,Operandisload-storeFP registeCan also be treated aModel 32 32-bit integer registers Actually 31: r0 is hardwired to value 0 wrsLO: destination registers for multiply/divideInteger register conventions Allows separate function-levels 16 64-bitFP registerscompilation andhy?fast function callsMemory AdISAs assume virtualISApoint? no roomdressing () Either 32 or 64 bits Program can name 232 bytes (4GB) or 264foraddress sizeevenone addressbytes (16PB)in a 32-bit instruction AMemory AdISAs assume virtual ISAddrepoint? no roomssing mode : way of Direct: ld R1,(R2)Displacement: ldIndexed: ldMemory-indirect: ldAuto-update:dressi Either 32 or 64 bits Program can name 232 bytes (4GB) or 264ld R1,8(R2) Scaled: ld R1,(R2,R3,32,8)forng (address sizeevenR1,8(R2)R1,(R2,R3)one addre)ssspecifying address R1=mem[R2]R1=mem[R2+R1,@(R2)bytes (16PB)in a 32-bit insR1=mem[R2+R3]R1R2=mem[mem[R2]]+=8; R1=mem[R2]R1=mem[R2+R3*32+8]truction8] AMemory AdISAs assume virtual ISAddrepoint? no roomssing mode : way of Direct: ld R1,(R2)Displacement: ldIndexed: ldMemory-indirect: ldAuto-update:dressing ( Either 32 or 64 bits Program can name 232 bytes (4GB) or 264ld R1,8(R2) Scaled: ld R1,(R2,R3,32,8)What high-level program idioms areforaddress sizeevenR1,8(R2)R1,(R2,R3)one addreR1,@(R2))ssspecifying address R1=mem[R2]R1=mem[R2+bytes (16PB)in a 32-bit insR1=mem[R2+R3]R1R2=mem[mem[R2]]+=8; R1=mem[R2]R1=mem[R2+R3*32+8]these used for?truction8] MIPMIPSS 80% useAddressingimplMoements only displacementdes: Rationality Why? Experiment on VAX (ISA with every mode) found distribution Disp: 61%, reg-ind: 19%, scaled: 11%, mem-ind: 5%, other: 4%displacement or register indirect (=displacement0)MIPMIPSS 80% useAddressingimplMoements only displacementdes: Rationality Why? Experiment on VAX (ISA with every mode) found distribution Disp: 61%, reg-ind: 19%, scaled: 11%, mem-ind: 5%, other: 4%displacement or register indirect (=displacementHow about the remain 20%?0)MIPMIPSS 80% useAddressingimplI-type instructions: 16-bit displacement Is 16-bits enough? Yes! VAX eI-typeMoements only displacementxperiment showedOp(6)Rs(5)des: Rationality Why? Experiment on VAX (ISA with every mode) found distribution Disp: 61%, reg-ind: 19%, scaled: 11%, mem-ind: 5%, other: 4%displacement or register indirect (=Rt(5)1% accessesdisplacementImmed(16)use displacement >16
0)
M
IP
MIPS
S
80% use
Addressing
impl
I-type instructions: 16-bit displacement Is 16-bits enough?
Yes! VAX e
I-typ
e
Mo
ements only displacement
xperiment showed
Op(6)
Rs(5)
des: Rationality
Why? Experiment on VAX (ISA with every mode) found distribution
Disp: 61%, reg-ind: 19%, scaled: 11%, mem-ind: 5%, other: 4%
displacement or register indirect (=
Rt(5)
1% access
es
displacement
Immed(16)
us
e displacement >16
0)
Addressing
Byte Order ()
Littl
Vax,
e En
Issue: E
dian: byte 0 is 8 least sig
DEC/Compaq Alpha
ndian-ness
Big Endian: byte 0 is 8 most significant bits IBM Motorola 68k, MIPS, SPARC, HP PA-RISC
nificant bits
360/370,
Intel 8086, DEC
Addressing
Alignment: require that
is multiple of their size
32-bit intege
Alig
Alig
ned if
ned: lw
Not:lw@XX
r
Issue: Alignm
address % 4 =
@XXXX
XX10
00
objec
ts fall
ent
on address that
0 [% is symbol for mod]
Aligned
Not
0
1
Byte #
2
3
Another Addressing Iss
Alignment: require that
is multiple of their size
32-bit intege
Alig
Alig
ned if
ned: lw
Not:lw@XX
Que
stion:
(uncommon
r
address % 4 =
what
Support in hardware?
@XXXX
XX10
to
case)?
Trap to software routine? Possibility
MIPS? ISA sup
instructions:
lw
@X
XXX10 = l
00
do with
wl
objec
ue: Alig
ts fall
0 [% is symbol for mod]
unaligned acces
Makes all accesses slow
port: unaligned access using two
@XXXX10;
lwr
nment
on address that
ses
@XXX
Aligned
X10
Not
0
1
Byte #
2
3
5. Datatypes
Dat
atypes
Software view: property of data
Hardware view: data is just bits, property of opera
tions
5. Datatypes
Dat
atypes
Software view: property of data
Hardware view: data is just bits, property of opera
Hardware
Integer: 8 bits
datatypes
(byte), 16b
(half), 3
IEEE754 FP: 32b (single-precision), 64b (double-precision)
Packed integer: treat 64b int as 8 8b ints or 4 16b ints
2b
(word),
64b (lon
tions
g)
MIPS
Dat
Datatypes
atypes: a
All integer operations rea
ll the b
No partial dependenc
Only byte/half variants are load-store
lb, lbu, lh, lhu, sb, sh
Loads sign-extend (or not) byte/half
(and Operations)
asic
ones (byte,
d/writ
es
on
e 32-bits
re
gisters
half, word,
into 32-bits
FP)
MIPS
Dat
Datatypes
atypes: a
All integer operations rea
ll the b
No partial dependenc
Only byte/half variants are load-store
lb, lbu, lh, lhu, sb, sh
Loads sign-extend (or not) byte/half
Operations: all
Signed/unsigned varia
Immediate variants for
th
add, addu, addi, addiu
(and Operations)
asic
e basic o
Regularity/orthogonality: all variants Makes compilers life easier
ones (byte,
d/writ
es
on
nes
e 32-bits
re
gisters
nts for integer arithmetic all instructions
half, word,
into 32-bits
available for all operations
FP)
6.1
C
ontrol
One issue: testing f
subi
bn
Instructions
$2,$1,10
target
Option III: condition registers, s
or
Option I: compare and branch instructions blti $1,10,target
I
conditions
+
Simple,
t
wo ALUs: one for c
Option II: implicit condition codes
ondition, one
sets negative
+ Condition codes set for free, implicit dependence is tricky
eparate
br
an
for
ch
target a
insns
ddress
//
CC
slti
bnez
Additional ins
$2,$1,10
$2,target
tru
ctions, + one AL
U per
,+
explicit dependence
M
IP
MIPS
S
Conditional Branch
uses c
Compare 2
Compare 1
+ Set
Why?
Gr
ombination
registers and
Equality and inequality only
+
Dont
need an adder for
register
to
eater/less than comparisons
Dont need adder for comparison
explicit condition registers: slt, sltu, slti,
es
of options II and III
branch:
compari
zero and branch: b
beq,
son
bne
gt
z, bgez, bltz, blez
sltiu,
etc.
M
IP
MIPS
S
Conditional Branch
uses c
Compare 2
Compare 1
+ Set
Why?
compari
Gr
ombination
registers and
Equality and inequality only
+
Dont
need an adder for
register
to
eater/less than comparisons
branch:
es
of options II and III
compari
zero and branch: b
Dont need adder for comparison
explicit condition registers: slt, sltu, slti,
86% of branch
sons to 0
beq,
son
bne
gt
es in programs are (in)equalities or
z, bgez, bltz, blez
sltiu,
etc.
6.2
Another
C
Option I:
ontrol
issu
Position
Needed
Used
Instructions
e:
PC-relativ
com
-independent
puting targets
e
es
an
II
within procedure
d jum
for jumping to dynamic targets
for returns
, dynamic pro
ps
within a
procedure
re
cedure calls, switches, ???
Used for branch
Option II: Absolute
Position independent outside procedu
Used for procedure calls
Option III: Indirect (target found in register)
Control
Another
Option I:
Instructions
issu
Position
Needed
Used
How far do
Ty
Fu
pically n
rth
e:
PC-relativ
com
-independent
es
II
puting targets
e
an
within procedure
d jum
for jumping to dynamic targets
for returns
ot so
er from one proced
, dynamic pro
you need to jump?
far
ps
within a
procedure
re
cedure calls, switches, ???
within a procedure (they dont get t
ure to anot
her
hat big)
Used for branch
Option II: Absolute
Position independent outside procedu
Used for procedure calls
Option III: Indirect (target found in register)
Control
Another
Option I:
Instructions
issu
Position
Needed
Used
How far do
Ty
pically n
Furth
e:
PC-relativ
computi
-independent
e
es
II
an
ng targets
within procedure
d jum
for jumping to dynamic targets
for returns
, dynamic pro
you need to jump?
ot so
far
ps
within a
within a procedure (they dont get t
er from one procedure to another
procedure
re
cedure calls, switches
hat big)
Used for branch
Option II: Absolute
Position independent outside procedu
Used for procedure calls
Option III: Indirect (target found in register)
M
IP
MIPS
S
PC-relati
Control
uses all thr
PC =
ve
Instructions
co
ee
nditio
nal branches: bne,
16-bit relative offset, <0.1% branches need morePC + 4 + immediate if condition is true (else Pbeq,blez, etc.C=PC+4) AbsoluteI-typeOp(6)Rs(5)unconditional jumps: 26-bit offset (can address 228Rt(5)jImmed(16)targetwords < 232 what gives?) J-type IndirectIndirect jumR-typeOp(6)Op(6)ps:jr $rdRs(5)Rt(5)Target(26) Rd(5)Sh(5)Func(6)6.3Another WePCControlissuInstructionse:howtoIIIsupport procedlink (remember) address of the calling instruction + 4 (curren+ 4) so we can return to it after the procedureure calls?t ControlAnother We PCMIPSImplicit retuInstructionsissue:howrn address Direct jump-and-link: jal address $ra = PC+4; PC = address Can then return from calltoIIIsupport procedlink (remember) address of the calling instruction + 4 (curren + 4) so we can return to it after the procedureregisterwith:is$rjr $raa(=$ure calls?31)tControlAnother We PCMIPSImplicit retuInstructionsissu Can then return from calle:howrn address Direct jump-and-link: jal address $ra = PC+4; PC = address Or can call with indirect jump-and-link:$rd = PC+4; Then return with:toPC = $rsjr $rdIIIsupport procedlink (remember) address of the calling instruction + 4 (curren + 4) so we can return to it after the procedureregisterwith:is$rjr $raa(=$// explicit return addreure calls?31)jalr $rd,ss$rsregistertControl:If-Then-ElseUnderstandingprograms helps with architecture Knowwhatcommon programming idiomslook like in assembly Why?Howcan youMCCF if youdontknowwhatCC is? Control:Understanding Know Why?whatHowIf-Then-Ecommon programming idiomscan yFirst control idiom: if -then -elseifelse(A < B)B++;What’sA++;theouMCCF if youM////IPSlseprograms helps with aABdontin $s1in $s2format?rchitectureknowlook like in assemblywhatCC is? Control:Understanding Know Whifelsey?(A < B)whatHowB++;else: join:can ysltIf-Then-EFirst control idiom: if -then -elseA++;ouMCCF if you$s3,$s1,$s2beqz $s3,elseaddi $s1,$s1,1j joinaddi $s2,$s2,1////lseprograms helps with acommon programming idiomsABdontin $s1in $s2// if$s// branch torchitectureknowlook like in assemblywhat1<$s2, t// jump to joinCC is?hen $s3=1else if !condition Control:Secondidiom:int A[100], sum,for (i=0; i
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