[SOLVED] MIPS assembly MIPS R2000 Assembly Language

MIPS R2000 Assembly Language
Arithmetic and Logical Instructions
Instruction
Format
Comment
Absolute value
abs rdest, rsrc
pseudoinstruction
Put the absolute value of register rsrc in register rdest
Addition (with overflow)
add rd, rs, rt
0
0
rs
rt
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rd
0
0x20
Addition (without overflow)
addu rd, rs, rt
rs
rt
rd
0
0x21
Put the sum of the register rs and rt into register rd
655556
Addition immediate (with overflow) addi rt, rs, imm
8
rs
655
rt
imm
16
Addition immediate (without overflow) addiu rt, rs, imm
9
rs
rt
imm
Put the sum of register rs and the sign-extended immediate into register rt
655
16
AND
and rd, rs, rt
0
rs
rt
655556
rd
0
0x24
Put the logical AND of register rs and rt into register rd
AND immediate
andi rt, rs, imm
Put the logical AND of register rs and the zero-extended immediate into register rt
0xc
rs
rt
imm
655
16
Divide (with overflow)
div rs, rt
0
rs
rt
0
0x1a
655
10
6
Divide (without overflow)
divu rs, rt
0
rs
655
rt
0
10
0x1b
6
Divide register rs by register rt. Leave the quotient in register lo and the remainder in register hi. If an operand is negative, the remainder is unspecified by the MIPS architecture and depends on the convention of the machine on which SPIM is run.
Divide (with overflow)
div rdest, rsrc1, src2
pseudoinstruction
Divide (without overflow)
div rdest, rsrc1, src2
pseudoinstruction
Put the quotient of register rsrc1 and src2 into register rdest.
Multiply
mult rs, rt
0
rs
rt
0
0x18
655
0
rs
655
rt
10
0
10
6
Unsigned multiply
multu rs, rt
0x19
6
Multiply registers rs and rt. Leave the low-order word of the product in register lo and the high-order word in register hi

Multiply (without overflow) pseudoinstruction mul rdest, rsrc1, src2
Multiply (with overflow)
mulo rdest, rsrc1, src2
pseudoinstruction
Unsigned multiply (with overflow)
mulou rdest, rsrc1, src2
pseudoinstruction
Put the product of register rsrc1 and src2 into register rdest.
Negate value (with overflow)
neg rdest, rsrc
pseudoinstruction
Negate value (without overflow)
negu rdest, rsrc
pseudoinstruction
Put the negative of register rsrc into register rd.
NOR
nor rd, rs, rt
0
rs
rt
rd
0
0x27
Put the logical NOR of registers rs and rt into register rd
655556
NOT
not rdest, rsrc
pseudoinstruction
Put the bitwise logical negation of register rsrc into register rdest.
OR
or rd, rs, rt
0
rs
rt
rd
0
0x25
Put the logical OR of registers rs and rt into register rd.
655556
OR immediate
ori rt, rs, imm
0xd
rs
rt
imm
655
16
Put the logical OR of register rs and the zero-extended immediate into register rt.
Remainder
rem rdest, rsrc1, rsrc2
pseudoinstruction
Unsigned remainder
rem rdest, rsrc1, rsrc2
pseudoinstruction
Put the remainder of register rsrc1 divided by register rsrc2 into register rdest. If an operand is negative, the remainder is unspecified by the MIPS architecture and depends on the convention of the machine on which SPIM is run.
Shift left logical
sll rd, rt, shamt
0
rs
rt
rd
shamt
0
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Shift left logical variable
sllv rd, rt, rs
0
rs
rt
rd
0
4
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Shift right arithmetic
sra rd, rt, shamt
0
rs
rt
rd
shamt
3
655556
Shift right arithmetic variable
srav rd, rt, rs
0
rs
rt
rd
0
7
655556
Shift right logical
srl rd, rt, shamt
0
rs
rt
rd
shamt
2
655556

0
rs
rt
rd
0
6
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Shift right logical variable
srlv rd, rt, rs
Shift register rt left (right) by the distance indicated by the immediate shamt or the register rs and put the result into register rd. Argument rs is ignored for sll, sra, and srl.
Rotate left
rol rdest, rsrc1, rsrc2
pseudo-instruction
Rotate right
ror rdest, rsrc1, rsrc2
pseudo-instruction
655
0
655
rt
rt
imm
16
Rotate register rsrc1 left (right) by the distance indicated by rsrc2 and put the result into register rdest.
Subtract (with overflow)
sub rd, rs, rt
0
rs
rt
rd
0
0x22
655556
Subtract (without overflow)
subu rd, rs, rt
0
rs
rt
rd
0
0x23
Put the difference of registers rs and rt into register rd.
655556
Exclusive OR
xor rd, rs, rt
0
rs
rt
rd
0
0x26
Put the logical XOR of registers rs and rt into register rd.
655556
XOR immediate
xori rt, rs, imm
0xe
rs
Put the logical XOR of register rs and the zero-extended immediate into register rt.
Constant-Manipulating Instructions
Load upper immediate
lui rt, imm
0xf
imm
16
Load the lower halfword of the immediate imm into the upper halfword of register rt. The lower bits of the register are set to 0.
Load immediate
li rdest, imm
pseudoinstruction
Move the immediate imm into register rdest.
Comparison instructions
Set less than
slt rd, rs, rt
0
rs
rt
rd
0
0x2a
655556
Set less than unsigned
sltu rd, rs, rt
0
rs
rt
655556
rd
0
0x2b
Set register rd to 1 if register rs is less than rt, and to 0 otherwise.
Set less than immediate
slti rd, rs, imm
0xa
rs
rd
imm
655
16
Set less than unsigned immediate
sltiu rd, rs, imm
Set register rd to 1 if register rs is less than the sign-extended immediate, and to o otherwise.
0xb
0
rt
imm
655
16
Set equal
seq rdest, rsrc1, rsrc2
pseudoinstruction
Set register rdest to 1 if register rsrc1 equals rsrc2, and to 0 otherwise.

Set greater than equal
sge rdest, rsrc1, rsrc2
pseudoinstruction
Set greater than equal unsigned
sgeu rdest, rsrc1, rsrc2
pseudoinstruction
Set register rdest to 1 if register rsrc1 is greater than or equal to register rsrc2, and to 0 otherwise.
Set greater than
sgt rdest, rsrc1, rsrc2
pseudoinstruction
Set greater than unsigned
sgtu rdest, rsrc1, rsrc2
pseudoinstruction
Set register rdest to 1 if register rsrc1 is greater than register rsrc2, and to 0 otherwise.
Set less than equal
sle rdest, rsrc1, rsrc2
pseudoinstruction
Set less than equal unsigned
sleu rdest, rsrc1, rsrc2
Branch instructions
pseudoinstruction
Set register rdest to 1 if register rsrc1 is less than or equal to rsrc2, and to 0 otherwise.
Branch instruction
b label
pseudoinstruction
Unconditionally branch to the instruction at the label.
Branch coprocessor z true
bczt label
0x1z
8
1
offset
655
16
Branch coprocessor z false
bczf label
0x1z
8
655
0
offset
16
Conditionally branch the number of instructions specified by the offset if zs condition flag is true (false). z is 0, 1, 2, or 3. The floating point unit is z = 1.
Branch on equal
beq rs, rt, label
4
rs
655
rt
offset
16
Conditionally branch the number of instructions specified by the offset if register rs equals rt.
Branch on greater than equal zero
bgez rs, label
1
rs
655
655
1
offset
Conditionally branch the number of instructions specified by the offset if register rs is greater than or equal to 0.
16
Branch on greater than equal zero and link bgezal rs, label
Conditionally branch the number of instructions specified by the offset if register rs is greater than or equal to 0. Save the address of the next instruction in register 31.
1
rs
0x11
offset
16
Branch on greater than zero
bgtz rs, label
Conditionally branch the instructions specified by the offset if register rs is greater than 0.
7
rs
0
offset
655
16

Branch on less than equal zero
blez rs, label
Conditionally branch the instructions specified by the offset if register rs is less than or equal to 0.
6
rs
0
offset
655
16
Branch on less than zero and link
bltzal rs, label
1
rs
0x10
offset
655
16
Conditionally branch the instructions specified by the offset if register rs is less than 0. Save the address of the next instruction in register 31.
Branch on less than zero
bltz rs, label
1
rs
0
offset
655
16
Conditionally branch the instructions specified by the offset if register rs is less than 0.
Branch on not equal
bne rs, rt, label
5
rs
rt
offset
655
16
Conditionally branch the instructions specified by the offset if register rs is not equal to rt.
Branch on equal zero
beqz rsrc, label
pseudoinstruction
Conditionally branch to the instruction at the label if register rsrc equals 0.
Branch on greater than equal
bge rsrc1, rsrc2, label
pseudoinstruction
Branch on greater than equal unsigned
bgeu rsrc1, rsrc2, label
pseudoinstruction
Conditionally branch to the instruction at the label if register rsrc1 is greater than or equal to rsrc2.
Branch on greater than
bgt rsrc1, src2, label
pseudoinstruction
Branch on greater than unsigned
bgtu rsrc1, src2, label
pseudoinstruction
Conditionally branch to the instruction at the label if register rsrc1 is greater than src2.
Branch on less than equal
ble rsrc1, src2, label
pseudoinstruction
Branch on less than equal unsigned
bleu rsrc1, src2, label
pseudoinstruction
Conditionally branch to the instruction at the label if register rsrc1 is less than or equal to src2.
Branch on less than
blt rsrc1, src2, label
pseudoinstruction
Branch on less than unsigned
bltu rsrc1, src2, label
pseudoinstruction
Conditionally branch to the instruction at the label if register rsrc1 is less than src2.

Branch on not equal zero
bnez rsrc, label
pseudoinstruction
Conditionally branch to the instruction at the label if register rsrc is not equal to zero
Jump instructions
Jump
j target
2
6
target
Unconditionally jump to the instruction at target.
26
Jump and link
jal target
Unconditionally jump to the instruction at target. Save the address of the next instruction in register $ra.
3
target
6
26
Jump and link register
jalr rs, rd
Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31).
0
rs
0
rd
0
9
655556
Jump register
jr rs
Unconditionally jump to the instruction whose address is in register rs.
0
rs
0
0
0
8
655556
Load instructions
Load rdest, address
la rdest, address
pseudoinstruction
Load computed address not the contents of the location into register rd.
Load byte
lb rt, address
0x20
rs
rt
offset
655
16
Load unsigned byte
lbu rt, address
Load the byte at address into register rt. The byt is sign- extended by lb, but not by lbu.
0x24
rs
rt
offset
655
16
Load halfword
lh rt address
0x21
rs
rt
offset
655
16
Load unsigned halfword
lhu rt, address
0x25
rs
rt
offset
Load the byte at address into register rt. The byt is sign- extended by lh, but not by lhu.
655
16
Load word
lw rt, address
0x23
rs
655
rt
offset
Load 32-bit word at address into register rt.
16
Load word coprocessor
lwcz rt, address
0x3z
rs
rt
offset
Load the word at address into register rt of coprocessor z (0-3). The FP unit is z = 1.
655
16
Load word left
lwl rt, address
0x22
rs
rt
offset
655
16

Load word right
lwr rt, address
rs
rt
offset
Load the left (right) bytes from the word at the possibly unaligned address into register rt.
0x26
655
16
Load doubleword
ld rdest, address
pseudoinstruction
Load the 64-bit double word at address into registers rdest and rest + 1.
Unaligned load halfword
ulh rdest, address
pseudoinstruction
Unaligned load halfword unsigned
ulhu rdest, address
pseudoinstruction
Load the 16-bit halfword at the possibly unaligned address into register rdest. The halfword is sign-extended by ulh, but not ulhu.
Unaligned load word
ulw rdest, address
Store instructions
pseudoinstruction
Load the 32-bit word at the possibly unaligned address into register rdest.
Store byte
sb rt, address
0x28
rs
rt
offset
Store the low byte from register rt at address.
655
16
Store halfword
sh rt, address
0x29
rs
rt
offset
Store the low halfword from register rt at address.
655
16
Store word
sw rt, address
0x2b
rs
rt
offset
Store the word from register rt at address.
655
16
Store word coprocessor
swcz rt, address
Store the word from register rt of coprocessor z at address. The FP unit is z=1.
0x2z
rs
rt
offset
655
16
Store word left
swl rt, address
0x2a
rs
rt
offset
655
16
Store word right
swr rt, address
Store the left (right) bytes from register rt at the possibly unaligned address.
0x2e
rs
rt
offset
655
16
Store doubleword
sd rsrc, address
pseudoinstruction
Store the 64-bit double word in registers rsrc and rsrc+1 at address
Unaligned store halfword
ush rsrc, address
pseudoinstruction
Store the low halfword from register rsrc at the possibly unaligned address.
Unaligned store word
usw rsrc, address
pseudoinstruction
Store the word from register rsrc at the possibly unaligned address.

Data movement instructions
Move from hi
mfhi rd
0
0
0
rd
0
0x10
655556
Move from lo
mflo rd
0
0
0
rd
0
0x12
655556
The multiply and divide unit produces its results in two additional registers, hi and lo. These instructions move values to and from these registers.
Move the hi (lo) register to register rd.
Move to hi
mthi rs
0
rs
0
0
0
0x11
655556
Move to lo
mtlo rs
0
rs
0
0
0
0x13
Move register rs to the high (lo) register.
655556
Move from coprocessor z
mfcz rt, rd
0x1z
0
rt
rd
0
0
655556
Coprocessors have their own register sets. These instructions move values between these registers and the CPUs registers.
Move coprocessor zs register rd to CPU register rt. The FP unit is z=1.
Move double from coprocessor 1 mfc1.d rdest, frsrc1
pseudoinstruction
Move FP registers frsrc1 and frsrc1+1 to CPU registers rdest and rdest+1.
Move to coprocessor z
mtcz rd, rt
0x1z
4
rt
rd
0
0
Move CPU register rt to coprocessor zs register rd.
655556
FP instructions (vergl. Patterson/Hennessy: Computer Organization & Design)
Exception and interrupt instructions
Return from exception
rfe
0x10
1
0
0
0
0x20
Restore the status register.
619556
System call
syscall
0
0
0
0
0
0xc
655556
Register $v0 contains the number of the systems call provided by SPIM
Break
break code
0
code
0xd
Cause exception code. Exception 1 is reserved for the debugger.
6
20
6
No operation
nop
0
0
0
0
0
0
Do nothing
655556

MIPS Register und Konventionen fur die Verwendung der Register
Register name
Number
Usage
$zero
0
constant 0
$at
1
reserved for assembler
$v0
2
expression evaluation and results of a function
$v1
3
expression evaluation and results of a function
$a0
4
argument 1
$a1
5
argument 2
$a2
6
argument 3
$a3
7
argument 4
$t0
8
temporary (not preserved across call)
$t1
9
temporary (not preserved across call)
$t2
10
temporary (not preserved across call)
$t3
11
temporary (not preserved across call)
$t4
12
temporary (not preserved across call)
$t5
13
temporary (not preserved across call)
$t6
14
temporary (not preserved across call)
$t7
15
temporary (not preserved across call)
$s0
16
saved temporary (preserved across call)
$s1
17
saved temporary (preserved across call)
$s2
18
saved temporary (preserved across call)
$s3
19
saved temporary (preserved across call)
$s4
20
saved temporary (preserved across call)
$s5
21
saved temporary (preserved across call)
$s6
22
saved temporary (preserved across call)
$s7
23
saved temporary (preserved across call)
$t8
24
temporary (not preserved across call)
$t9
25
temporary (not preserved across call)
$k0
26
reserved for OS kernel
$k1
27
reserved for OS kernel
$gp
28
pointer to global area
$sp
29
stack pointer
$fp
30
frame pointer
$ra
31
return address (used by function call)
Reference: http://www.cs.wisc.edu/~larus/SPIM/cod-appa.pdf