In this laboratory, you will implement an electronic “Etch A Sketch” in RSRC assembly language starting with VHDL models for the RSRC CPU (rsrc.vhd), a Read-Only Memory (eprom.vhd), a Static Random-Access Memory (sram.vhd), a 1-bit vga display module (vga.vhd), and a button input module (buttons.vhd). Each of these components, as well as the assembly language syntax for the RSRC CPU, will be discussed in detail during class lectures.
The top level module you will implement and test, testbench.vhd, is a hierarchical “wrapper” that “wraps up” these components into a working embedded RSRC system.
The target platform for your electronic “Etch A Sketch” is the Digilent, Inc., development board used in labs 1 and 2. In this lab, the VGA output will be used to drive a VGA monitor operating in 640×480-pixel mode.
The system you implement should use the BTNR, BTNL, BTNU, and BTND buttons to draw lines moving to the left, right, up, and down, respectively. BTNC should “shake” the screen to erase it, leaving the drawing cursor at its last position.
For full credit, you must implement the ability to move at 45 degree angles!
For full credit, your program must never try to write to a non-existent framestore location (which will cause the program to hang due to the fact that DONE.H will not be asserted).
Since the embedded RSRC CPU will not run at 100 MHz, a divider circuit is included in the top level module to produce the 25 MHz clock (clk) needed for your embedded system. Make sure you understand how this is implemented and how the Digilent, Inc., board has to be configured for your demonstration.
Students electing not to attend lectures will need to review the VHDL source files provided to gain an understanding of how the embedded system is constructed, how the vga.vhd and buttons.vhd modules work, etc.
STEP 1
Create a new Vivado project following the steps below precisely.
Run Vivado, and select “Create Project” from the Quick Start menu.
Click “Next” on the “New Project” GUI screen that says “This wizard will guide you through the creation of a new project.”
Create a new project in a directory where you know for certain that you have read/write permission. This directory should be a directory you can find easily after you exit the Vivado CAD tool. You must use the project name “Lab 3” (please).
Make sure the “Create project subdirectory” box is checked. This is important.
Click “Next” to move to the “Project Type” screen.
Select “RTL Project” from the “Project Type” menu and select “Next” to move to the “Add Sources” screen.
This next step is where you will make a very serious mistake if you are not careful. After you click “Next” on the “Project Type” GUI menu shown on the previous page, Vivado creates the project directory (here, Lab 3) in the directory location you specified.
What you are required to do in this laboratory is to PLACE A COPY OF ALL OF THE SOURCE FILES PROVIDED BY THE INSTRUCTOR IN THE “Lab 3” project directory created by Vivado at exactly this point in the project creation process.
Before and after you place copies of the source files provided in the “Lab 3” directory, the Vivado GUI menu shown below will be displayed by the Vivado CAD tool.
You must use the Windows File Explorer to copy your files outside of Vivado into the Lab 3 project folder.
After, and only after, you have placed copies of the source files in the project directory, select the “Add Files” GUI button on the “Add Sources” GUI menu shown below.
At this point, you will need to navigate inside the Vivado tool to find the project directory created by Vivado and select the VHDL source files you copied into the project folder. You can select all of the VHDL source files at one time as shown below.
After you have selected all of the VHDL source files, click “OK” on the “Add Source Files” GUI menu to move to the next screen.
Make 100% sure that you have each VHDL source file set for “Synthesis & Simulation,” and be 200% sure the two check boxes shown circled below ARE NOT CHECKED!
If you follow the procedure outlined here, the only copies of the source files used by Vivado will be those in the project root directory (here, Lab 3). Vivado will not use remote copies, nor will it create new copies in the “sources” subdirectory of the “Lab 3” directory. All will be right with the world. Click “Next” to move to the “Add Constraints” GUI menu.
Select “Add Files” on the “Add Constraints” menu shown below and navigate to the “testbench.xdc” file you placed in the project folder.
Before you click “Next,” make 200% sure the check box circled in red below IS NOT CHECKED! By doing this, you make sure Vivado does not use a remote copy of the constraints file nor make a copy in the “sources” directory. This is extremely important!
Select the Artix-7 part used on the NEXYS 4 DDR board as you did in Lab 1 and Lab 2 and click “Next” to move to the “New Project Summary” GUI menu.
Double-check that you have selected the correct FPGA, that you have included all 18 VHDL source files and one constraint file, and then click “Finish” to create the full Vivado project.
At
At this point, if you have followed the project creation procedure outlined above precisely, you will have a Vivado project with all of the source and constraint files contained in a single “folder” or “directory” called “Lab 3.,” and none of the files will be in subfolders! This folder can be, and will be after you finish the laboratory, copied to a FLASH drive and easily transferred to another computer or to the instructor for grading.
An example of what your Vivado project should look like at this point in the process is shown on the next page.
STEP 2
Synthesize the design to make sure you have created the project correctly before continuing to Step 3. If you have errors during synthesis, you have made a mistake, e.g., not included a required source file. Any errors will have to be addressed before you continue to Step 3.
You will observe that synthesis does result in several warnings (you should see 103). This is not a problem as these warnings are the result of outputs of some of the hierarchical modules not being used in some of the other modules to which they are connected. You always want to look through any warnings you see, and not simply ignore them, as sometimes they indicate real problems. Look through the warnings you see here and take a minute to see if you can find out why a few of them are flagged as warnings.
STEP 3
The assembly code implemented in eprom.vhd file provided is shown below.
.org 0
lar r2,MYVGA ; r2 holds the frame buffer base address
la r29,BTN ; r29 holds the button module address
la r1,1 ; “Shake” the screen
la r31,LOOP1
lar r30,MYVGA ; Use the base address
LOOP1: st r1,0(r30) ; Write a pixel
addi r30,r30,4 ; Point to the next pixel
and r3,r30,r2 ; Check for the end of the framestore
brnz r31,r3 ; Repeat until r30 points past the framestore
lar r30,MYVGA ; Start in upper left corner
la r1,0 ; Set r1 to black
st r1,0(r30) ; Write upper left pixel black
stop
.org 2097152
MYVGA: .dw 524288
.org -4
BTN: .dw 1
This assembly program “shakes” the screen by writing the value 1 to the entire framestore. It then writes the value 0 to the first memory location in the framestore to indicate the starting point for the drawing cursor. To finish Lab 3, you have to write the rest of the assembly code!
The XCD constraints file provided by the instructor has the pins for clk, reset_l, the button inputs, and the VGA outputs constrained to the proper FPGA pins, so you could use Vivado to implement an embedded RSRC system that runs the program shown above by selecting “Run Implementation” and then “Generate Bitstream” as you did in Labs 1 and 2.
STEP 4
Write an assembly language program that implements the Etch A Sketch. Poll the buttons.vhd module register as discussed in class to know when to move the drawing stylus.
STEP 5
Verifying the correctness of your final assembly language program using the JAVA-based simulator is problematic: The “shake” portion will require a very long time to simulate, for example! And, the JAVA-based simulator cannot implement the button module functionality: While your program can read from the address associated with the button register, the value returned will always be the same.
You can, however, simulate the basic functionality of your program by removing, temporarily, the “shake” section of the code.
Simulate your program in the JAVA-based simulator and fix any bugs you find.
STEP 6
The instructor has written a simple C program (eprom.c) that reads an eprom.bin file (created by the JAVA-based simulator when it assembles an eprom.asm source file) and writes out an eprom.vhd file in the correct format to be used with the embedded RSRC system. The eprom.vhd file produced by this utility when used with the eprom.bin file for the assembly program above is shown on the next page.
The eprom.exe executable will be provided free of charge so that you can easily generate the eprom.vhd file you need to implement your embedded system. Here are a few helpful hints about the utility.
a) The syntax is simply “eprom” or “eprom.exe” (from a prompt), or double-click the file icon. The eprom.bin file must be in the same directory as the executable file (and it must be named exactly eprom.bin, not Eprom.bin or EPROM.BIN, for example).
b) The file eprom.bin is automatically opened, and you cannot specify another file.
c) The file eprom.vhd is created, overwriting any file in the directory with that name.
d) The “eprom” utility only supports assembly programs written to start at single address, e.g., with “.org 0” as the first line in the program. Additional .org statements placed after the main assembly program can be used to define the addresses of I/O registers, and this functionality has been tested and appears to work correctly.
As an alternative to using the “eprom” utility, you can create an eprom.vhd file from your eprom.bin file by hand, but that’s a lot of cut-and-paste!
Use the eprom.exe utility to create the eprom.vhd file you need to create your embedded RSRC system, and replace the eprom.vhd file in your “Lab 3” project directory with your new eprom.vhd file.
—2019 BIN-TO-VHD CONVERTER 1.0
—Copyright William D. Richard, Ph.D.
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY eprom IS
PORT (d : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ;
address : IN STD_LOGIC_VECTOR(9 DOWNTO 0) ;
ce_l : IN STD_LOGIC ;
oe_l : IN STD_LOGIC) ;
END eprom ;
ARCHITECTURE behavioral OF eprom IS
SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0) ;
SIGNAL sel : STD_LOGIC_VECTOR(31 DOWNTO 0) ;
BEGIN
sel <= “00000000000000000000” & address & “00” ; WITH sel SELECT data <= X”309ffffc” WHEN X”00000000″ , X”2f41fffc” WHEN X”00000004″ , X”28400001″ WHEN X”00000008″ , X”2fc00014″ WHEN X”0000000c” , X”379fffec” WHEN X”00000010″ , X”187c0000″ WHEN X”00000014″ , X”6fbc0004″ WHEN X”00000018″ , X”a0fc2000″ WHEN X”0000001c” , X”403e3003″ WHEN X”00000020″ , X”379fffd8″ WHEN X”00000024″ , X”28400000″ WHEN X”00000028″ , X”187c0000″ WHEN X”0000002c” , X”f8000000″ WHEN X”00000030″ , X”00000000″ WHEN OTHERS ; readprocess:PROCESS(ce_l,oe_l,data) begin IF (ce_l = ‘0’ AND oe_l = ‘0’) THEN d(31 DOWNTO 0) <= data ; else d(31 DOWNTO 0) <= (OTHERS => ‘Z’) ;
END IF;
END PROCESS readprocess ;
END behavioral ;
STEP 7
After replacing the original eprom.vhd file supplied by the instructor with the eprom.vhd file based on your RSRC assembly program, re-simulate your design using the Vivado simulator to make sure your program at least starts executing properly.
STEP 8
Implement your design and generate a BIT file you can use to demo with a TA.
When you implement your design, you will see that your implementation meets the timing constraints specified in the XDC constraints file. If your design does not meet the timing constraint, you’ve made a mistake somewhere along the way that will need to be corrected.
STEP 9
Print out a copy of your final commented assembly code to hand in when you test your lab.
Credit will not be given for an assembly language program that is not fully commented.
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