[SOLVED] C data structure MIPS assembly compiler LOGICAL AND BIT-FIELD OPERATIONS

LOGICAL AND BIT-FIELD OPERATIONS
AND RD, RS, RT
RD =RS &RT
ANDI RD, RS, CONST16
RD = RS & CONST16
EXTR2 RD, RS, P, S
RS = RSP+S-1:P
INSR2 RD, RS, P, S
RDP+S-1:P = RSS-1:0
NOP
NO-OP
NOR RD, RS, RT
RD = ~(RS | RT)
NOT RD, RS
RD = ~RS
OR RD, RS, RT
RD =RS |RT
ORI RD, RS, CONST16
RD = RS | CONST16
WSBHR2 RD, RS
RD = RS23:16 :: RS31:24 :: RS7:0 :: RS15:8
XOR RD, RS, RT
RD = RS RT
XORI RD, RS, CONST16
RD = RS CONST16
JUMPS AND BRANCHES (NOTE: ONE DELAY SLOT)
B OFF18
PC += OFF18
BAL OFF18
RA =PC+8,PC+=OFF18
BEQ RS, RT, OFF18
IF RS = RT, PC += OFF18
BEQZ RS, OFF18
IF RS = 0, PC += OFF18
BGEZ RS, OFF18
IF RS 0, PC += OFF18
BGEZAL RS, OFF18
RA =PC+8;IF RS 0,PC+=OFF18
BGTZ RS, OFF18
IF RS > 0, PC += OFF18
BLEZ RS, OFF18
IF RS 0, PC += OFF18
BLTZ RS, OFF18
IF RS < 0, PC += OFF18BLTZAL RS, OFF18RA =PC+8;IF RS <0,PC+=OFF18BNE RS, RT, OFF18IF RS = RT, PC += OFF18BNEZ RS, OFF18 IF RS = 0, PC += OFF18J ADDR28PC = PC31:28 :: ADDR28JAL ADDR28RA = PC + 8; PC = PC31:28 :: ADDR28JALR RD, RSRD =PC+8;PC=RSJR RSPC = RSRDRS, RT RAPC ACC LO, HI ::R2 DOTTEDMIPS32 Instruction Set Quick Reference DESTINATION REGISTER SOURCE OPERAND REGISTERS RETURN ADDRESS REGISTER (R31) PROGRAM COUNTER 64-BIT ACCUMULATOR ACCUMULATOR LOW (ACC31:0) AND HIGH (ACC63:32) PARTS SIGNED OPERAND OR SIGN EXTENSION UNSIGNED OPERAND OR ZERO EXTENSION CONCATENATION OF BIT FIELDS MIPS32 RELEASE 2 INSTRUCTION ASSEMBLER PSEUDO-INSTRUCTION PLEASE REFER TO MIPS32 ARCHITECTURE FOR PROGRAMMERS VOLUME II: THE MIPS32 INSTRUCTION SET FOR COMPLETE INSTRUCTION SET INFORMATION.ARITHMETIC OPERATIONSADD RD, RS, RTRD = RS + RT (OVERFLOW TRAP)ADDI RD, RS, CONST16RD = RS + CONST16 (OVERFLOW TRAP)ADDIU RD, RS, CONST16RD = RS + CONST16ADDU RD, RS, RTRD =RS +RTCLO RD, RSRD = COUNTLEADINGONES(RS)CLZ RD, RSRD = COUNTLEADINGZEROS(RS)LA RD, LABEL RD = ADDRESS(LABEL)LI RD, IMM32RD = IMM32 LUI RD, CONST16RD = CONST16 << 16MOVE RD, RS RD = RSNEGU RD, RS RD = RSSEBR2 RD, RSRD = RS7:0SEHR2 RD, RSRD = RS15:0SUB RD, RS, RTRD = RS RT (OVERFLOW TRAP)SUBU RD, RS, RTRD =RS RTCONDITION TESTING AND CONDITIONAL MOVE OPERATIONS MOVN RD, RS, RTIF RT =0,RD =RSMOVZ RD, RS, RTIF RT =0,RD =RSSLT RD, RS, RTRD =(RS > SHIFT5
SRAV RD, RS, RT
RD = RS >> RT4:0
SRL RD, RS, SHIFT5
RD = RS >> SHIFT5
SRLV RD, RS, RT
RD = RS >> RT4:0
Copyright 2008 MIPS Technologies, Inc. All rights reserved.
ACCUMULATOR ACCESS OPERATIONS
MFHI RD
RD = HI
MFLO RD
RD = LO
MTHI RS
HI = RS
MTLO RS
LO = RS
ATOMIC READ-MODIFY-WRITE OPERATIONS
LL RD, OFF16(RS)
RD = MEM32(RS + OFF16); LINK
SC RD, OFF16(RS)
IF ATOMIC, MEM32(RS + OFF16) = RD; RD =ATOMIC ?1:0
MD00565 Revision 01.01

REGISTERS
0
zero
Always equal to zero
1
at
Assembler temporary; used by the assembler
2-3
v0-v1
Return value from a function call
4-7
a0-a3
First four parameters for a function call
8-15
t0-t7
Temporary variables; need not be preserved
16-23
s0-s7
Function variables; must be preserved
24-25
t8-t9
Two more temporary variables
26-27
k0-k1
Kernel use registers; may change unexpectedly
28
gp
Global pointer
29
sp
Stack pointer
30
fp/s8
Stack frame pointer or subroutine variable
31
ra
Return address of the last subroutine call
READING THE CYCLE COUNT REGISTER FROM C
unsigned mips_cycle_counter_read()
{
unsigned cc;
asm volatile(mfc0 %0, $9 : =r (cc));
return (cc << 1);} ATOMIC READ-MODIFY-WRITE EXAMPLEatomic_inc:ll $t0, 0($a0)addiu $t1, $t0, 1sc $t1, 0($a0)beqz $t1, atomic_inc # loop if failed nop# load linked# increment# store cond’lASSEMBLY-LANGUAGE FUNCTION EXAMPLE # int asm_max(int a, int b) #{# int r = (a < b) ? b : a;# return r;#}asm_max:move $v0, $a0slt$t0, $a0, $a1jr $ramovn $v0, $a1, $t0.end asm_max.text.set nomacro.set noreorder.globalasm_max.ent asm_max# r = a# a < b ?# return# if yes, r = b ACCESSING UNALIGNED DATANOTE: ULW AND USW AUTOMATICALLY GENERATE APPROPRIATE CODE LITTLE-ENDIAN MODEBIG-ENDIAN MODELWR RD, OFF16(RS) LWL RD, OFF16+3(RS)LWL RD, OFF16(RS) LWR RD, OFF16+3(RS)SWR RD, OFF16(RS) SWL RD, OFF16+3(RS)SWL RD, OFF16(RS) SWR RD, OFF16+3(RS) ACCESSING UNALIGNED DATA FROM C typedef struct{int u;} __attribute__((packed)) unaligned;int unaligned_load(void *ptr){ unaligned *uptr = (unaligned *)ptr; return uptr->u;
}
DEFAULT C CALLING CONVENTION (O32)
Stack Management
The stack grows down.
Subtract from $sp to allocate local storage space.
Restore $sp by adding the same amount at function exit.
The stack must be 8-byte aligned.
Modify $sp only in multiples of eight.
Function Parameters
Every parameter smaller than 32 bits is promoted to 32 bits.
First four parameters are passed in registers $a0$a3.
64-bit parameters are passed in register pairs: Little-endian mode: $a1:$a0 or $a3:$a2.
Big-endian mode: $a0:$a1 or $a2:$a3.
Every subsequent parameter is passed through the stack.
First 16 bytes on the stack are not used.
Assuming $sp was not modified at function entry:
The 1st stack parameter is located at 16($sp).
The 2nd stack parameter is located at 20($sp), etc.
64-bit parameters are 8-byte aligned.
Return Values
32-bit and smaller values are returned in register $v0.
64-bit values are returned in registers $v0 and $v1:
Little-endian mode: $v1:$v0. Big-endian mode: $v0:$v1.
C / ASSEMBLY-LANGUAGE FUNCTION INTERFACE
#include
int asm_max(int a, int b);
int main()
{
int x = asm_max(10, 100);
int y = asm_max(200, 20);
printf(%d %d
, x, y);
}
MIPS SDE-GCC COMPILER DEFINES
__mips
MIPS ISA (= 32 for MIPS32)
__mips_isa_rev
MIPS ISA Revision (= 2 for MIPS32 R2)
__mips_dsp
DSP ASE extensions enabled
_MIPSEB
Big-endian target CPU
_MIPSEL
Little-endian target CPU
_MIPS_ARCH_CPU
Target CPU specified by -march=CPU
_MIPS_TUNE_CPU
Pipeline tuning selected by -mtune=CPU
INVOKING MULT AND MADD INSTRUCTIONS FROM C
int dp(int a[], int b[], int n)
{
int i;
long long acc = (long long) a[0] * b[0];
for (i = 1; i < n; i++) acc += (long long) a[i] * b[i];return (acc >> 31);
}
NOTES
Many assembler pseudo-instructions and some rarely used machine instructions are omitted.
The C calling convention is simplified. Additional rules apply when passing complex data structures as function parameters.
The examples illustrate syntax used by GCC compilers.
Most MIPS processors increment the cycle counter every other
cycle. Please check your processor documentation.
MIPS32 VIRTUAL ADDRESS SPACE
kseg3
0xE000.0000
0xFFFF.FFFF
Mapped
Cached
ksseg
0xC000.0000
0xDFFF.FFFF
Mapped
Cached
kseg1
0xA000.0000
0xBFFF.FFFF
Unmapped
Uncached
kseg0
0x8000.0000
0x9FFF.FFFF
Unmapped
Cached
useg
0x0000.0000
0x7FFF.FFFF
Mapped
Cached
Copyright 2008 MIPS Technologies, Inc. All rights reserved. MD00565 Revision 01.01