[SOLVED] assembly RSRC LAB 3 TESTBENCH BLOCK DIAGRAM

RSRC LAB 3 TESTBENCH BLOCK DIAGRAM
Copyright William D. Richard, Ph.D. November 12, 2019
The RSRC lab 3 embedded RSRC CPU system consists of the following VHDL components/modules: 0) CLK DIVIDER CODE
1) RESET_L SYNCHRONIZER CODE (ALWAYS!)
2) RSRC
3) EPROM 4) SRAM
5) VGA
6) BUTTONS
In order to keep the design as simple as possible, the 100 MHz clock used in Lab 2 is divided by four (4) to create a new 25 MHz clock for Lab 3. The code for this clock divider is included in the testbench.vhd file, at the top, right after BEGIN in the architecture section. The output CLK25 is routed out of the FPGA on pin H14 and back in on pin H16 as the new system CLK signal. Pin E3 is redefined, for Lab 3, as CLK100. A jumper is placed on header JB to connect pins H14 and H16.
The main inputs to the top-level testbench.vhd module are clk, reset_l (unsynchronized), and the five (5) button inputs BTNL, BTNR, BTNU, BTND, and BTNC, and the outputs are the outputs R(3:0), G(3:0), B(3:0), and HS and VS that connect to the VGA connector on the development board.
A block diagram of the testbench.vhd wrapper is shown on the next page. This block diagram corresponds fairly accurately with the actual VHDL found in testbench.vhd, with only a few exceptions:
a) The reset_l synchronizer implemented in testbench.vhd is not shown in the diagram;
b) The READ.L and WRITE.H signals shown on the block diagram are accurate, but in the VHDL each sub- module (SRAM, EPROM, VGA, and BUTTONS) each have their own named version of these signals. But, the diagram is accurate relative to functionality.
When implemented using the Vivado tools, the embedded RSRC CPU boots from the EPROM, can read and write the SRAM, and can poll the buttons module.
The VGA module, which will also be described in detail in class, implements a 1-bit VGA subsystem. The RSRC can write to and read from the 1-bit VGA framestore memory inside the VGA module.
In lab 3, students write an RSRC assembly program to implement an electronic Etch A Sketch using the five (5) button inputs to control the lines drawn on the 1-bit VGA display.

RESET_L_SYNC
32
READ.L
CLK
WRITE.L SRAM_CE.L
CLK
A<31..13> A<12> READ.H WRITE.H
19
20 READ.H
10
A<31..12>
A<31..22> A<21> READ.H WRITE.H
30 READ.H
READ.L
BUTTONS_CE.L CLK
A<31..2>
RSRC
32
A<11..2> 10 SRAM
A<31..0>
D<31..0> READ.H
WRITE.H DONE.H
TIMER_CE_L SEG7_CE_L
READ.L WRITE.L
VGA_ENA CLK
TIMER D<31..0>
A(20:2) D<31..0>
VGA
11
RESET_L_SYNC
EPROM
READ.L EPROM_CE.L
A<11..2> D<31..0> 32
10
5