[SOLVED] 1Kx32 Sync SRAM RSRC Memory

1Kx32 Sync SRAM RSRC Memory
Copyright William D. Richard, Ph.D. Updated November 26, 2018
The RSRC fetches instructions from external memory. It also stores calculated values in external memory and uses external memory for temporary storage not all of the variables of larger programs fit in 32 registers!
In CSE 362M, we investigate all types of memory, from simple asynchronous Static Random Access Memory (SRAM) to Dynamic RAM (DRAM). Here, we only need to understand the concept of memory in order to understand how the RSRC (and microprocessors in general) execute programs. Memory hierarchies, cache memory, etc., will simply have to wait (and are a big reason to take CSE 362M!).
The block diagram of a simple 1Kx32 synchronous SRAM we could use with the RSRC is shown below in Figure 1:
Figure 1. Symbol for a 1Kx32 synchronous SRAM with 4KB of memory.
The SRAM shown in Figure 1 contains 4096 bytes (4KB) of storage, or 1024 32-bit words. The industry- standard designation for a memory like this would be 1Kx32, not 4Kx32. When an address is presented to the SRAM and CE.L and OE.L are asserted low, this SRAM outputs the addressed word on the D<31..0> pins. When CE.L and WE.L are asserted low and data is driven onto the D<31..0> pins, that data is written to the addressed location at the rising clock edge. If CE.L is high, both OE.L and WE.L are ignored. In standard operation, OE.L and WE.L are never both asserted low at the same time.
One (very inefficient) way to implement the 1Kx32 synchronous SRAM of Figure 1 using D-type FFs is shown below in Figure 2. In practice, this approach to building an SRAM is far too expensive: This approach is only used here to explain the concept of memory. Real SRAMs are made using the industry- standard six-transistor memory cell or a more advanced memory cell technology.
10
32

Figure 2. Conceptual design of a 1Kx32 synchronous SRAM.
While the memory of Figure 2 would not be built in practice, it does use the same control signals and timing protocol as a real synchronous SRAM*. In Figure 3 below, this SRAM is shown connected to an RSRC CPU. Decoding logic is used to map the 4KB of memory into the physical address space of the RSRC. Since all of the upper address lines must be zero for the SRAM to be selected, the SRAM occupies the lower 4KB of the memory space. DONE.H is generated by the decoding logic, too, so that the RSRC leaves state S1 immediately during instruction fetch, for example, and continues to state S2.

RSRC
32
A<31..0>
READ.H
WRITE.H
32
A<11..2>
10
SRAM
DONE.H
CLK
CLK
Figure 3. Decoding logic is used to connect the 1Kx32 SRAM to the RSRC. Here, the 1Kx32 SRAM maps to the bottom 4KB of the RSRC physical memory space. Note that address lines A<11..2> connect to the SRAM A<9..0> address pins because the RSRC address is a byte address, and the RSRC reads four bytes at a time!
The timing diagram below illustrates the operation of the RSRC memory system. Initially, the RSRC asserts READ.H along with the address. In response, the memory subsystem responds with the data at the requested address and also asserts DONE.H to terminate the memory access cycle. The RSRC captures the data in the input MD register on the rising clock edge when DONE.H is asserted.
When the RSRC writes data to memory, it asserts WRITE.H along with both the address and the data to be written, and in response the memory subsystem asserts DONE.H to terminate the cycle and writes the data to the addressed memory location on the rising clock edge when DONE.H is asserted.
n
Figure 4. Timing diagram illustrating the operation of the RSRC memory subsystem.
A<31..12>
20
READ.H WRITE.H
CLK
WRITE.H
rd ad
wr ad
A<31..0> READ.H
do
ut
di
D<31..0>
DONE.H

A VHDL description of the synchronous SRAM of Figure 2 is shown below in Figure 5.
2018 new sram VHDL Code
Current file name: sram.vhd
Last Revised:8/22/2018; 2:47 p.m.
Author:WDR
Copyright:William D. Richard, Ph.D.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY sram IS
PORT (d
address
ce_l :IN oe_l :IN we_l :IN clk :IN
: INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) ;
:IN
STD_LOGIC_VECTOR(9 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC) ;
END sram ;
ARCHITECTURE behavioral OF sram IS
TYPE memoryarray IS ARRAY(1023 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0) ;
SIGNAL myarray : memoryarray ;
SIGNAL myindex : INTEGER RANGE 0 TO 1023 ;
SIGNAL temp : UNSIGNED(9 DOWNTO 0) ;
BEGIN
temp <= UNSIGNED(address(9 DOWNTO 0)) ; myindex <= CONV_INTEGER(temp) ; writeprocess:PROCESS(clk) beginIF (clk = ‘1’ AND clk’event) THEN IF (ce_l = ‘0’ AND we_l = ‘0’) THENmyarray(myindex) <= d(31 DOWNTO 0); END IF;END IF; END PROCESS writeprocess ; readprocess:PROCESS(ce_l,oe_l,myarray,myindex) beginIF (ce_l = ‘0’ AND oe_l = ‘0’) THEN d(31 DOWNTO 0) <= myarray(myindex) ;elsed(31 DOWNTO 0) <= (OTHERS => Z) ;
END IF;
END PROCESS readprocess ;
END behavioral ;
Figure 5. Synthesizable VHDL description of the synchronous SRAM show in Figure 2. This VHDL model is used with the RSRC testbench.vhd file to implement an embedded RSRC system in lab 3.
*A typical real synchronous SRAM registers the data output so that the addressed data word is only driven out of the SRAM after the rising clock edge when CE_L and OE_L are both asserted.