[Solved] Computer Organization Homework4 -RISC-V CPU

The goal of this homework is to help you understand how a single-cycle RISC-Vwork and how to use Verilog hardware description language (Verilog HDL) to modelelectronic systems. In this homework, you need to implement ALU and decodermodule and make your codes be able to execute all RISC-V instructions. You need tofollow the instruction table in this homework and satisfy all the homeworkrequirements. In addition, you need to verify your CPU by using Modelsim.General rules for deliverables You need to complete this homework INDIVIDUALLY. You can discuss thehomework with other students, but you need to do the homework by yourself.You should not copy anything from someone else, and you should notdistribute your homework to someone else. If you violate any of these rules,you will get NEGATIVE scores, or even fail this course directly When submitting your homework, compress all files into a single zip file,and upload the compressed file to Moodle. Please follow the file hierarchy shown in Figure 1.F740XXXXX ( your id ) (folder)src ( folder ) * Store your source codereport.docx ( project report. The report template is alreadyincluded. Follow the template to complete the report. )F740XXXXX/src/report.docxYour source codeYour source codeFigure 1. File hierarchy for homework submission Important! DO NOT submit your homework in the last minute. Latesubmission is not accepted. You should finish all the requirements (shown below) in this homework andProject report. If your code can not be recompiled by TA successfully using modelsim, youwill receive NO credit. Verilog and SystemVerilog generators arent allowed in this course.Instruction format: R-type31 25 24 20 19 15 14 12 11 7 6 0funct7 rs2 rs1 funct3 rd opcode Mnemonic Description0000000 rs2 rs1 000 rd 0110011 ADD rd = rs1 + rs20100000 rs2 rs1 000 rd 0110011 SUB rd = rs1 rs20000000 rs2 rs1 001 rd 0110011 SLL rd = rs1u << rs2[4:0]0000000 rs2 rs1 010 rd 0110011 SLT rd = rs1s < rs2s ? 1 : 00000000 rs2 rs1 011 rd 0110011 SLTU rd = rs1u < rs2u ? 1 : 00000000 rs2 rs1 100 rd 0110011 XOR rd = rs1 ^ rs20000000 rs2 rs1 101 rd 0110011 SRL rd = rs1u >> rs2[4:0]0100000 rs2 rs1 101 rd 0110011 SRA rd = rs1s >> rs2[4:0]0000000 rs2 rs1 110 rd 0110011 OR rd = rs1 | rs20000000 rs2 rs1 111 rd 0110011 AND rd = rs1 & rs2 I-type31 20 19 15 14 12 11 7 6 0imm[11:0] rs1 funct3 rd opcode Mnemonic Descriptionimm[11:0] rs1 010 rd 0000011 LW rd = M[rs1 + imm]imm[11:0] rs1 000 rd 0010011 ADDI rd = rs1 + immimm[11:0] rs1 010 rd 0010011 SLTI rd = rs1s < imms? 1:0imm[11:0] rs1 011 rd 0010011 SLTIU rd = rs1u < immu? 1:0imm[11:0] rs1 100 rd 0010011 XORI rd = rs1 ^ immimm[11:0] rs1 110 rd 0010011 ORI rd = rs1 | immimm[11:0] rs1 111 rd 0010011 ANDI rd = rs1 & imm0000000 shamt rs1 001 rd 0010011 SLLI rd = rs1u << shamt0000000 shamt rs1 101 rd 0010011 SRLI rd = rs1u >> shamt0100000 shamt rs1 101 rd 0010011 SRAI rd = rs1s >> shamtimm[11:0] rs1 000 rd 1100111 JALRrd = PC + 4PC = imm + rs1(Set LSB of PC to 0) S-type31 25 24 20 19 15 14 12 11 7 6 0imm[11:5] rs2 rs1 funct3 imm[4:0] opcode Mnemonic Descriptionimm[11:5] rs2 rs1 010 imm[4:0] 0100011 SW M[rs1 + imm] = rs2

B-type31 25 24 20 19 15 14 12 11 7 6 0imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode Mnemonic Descriptionimm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 BEQPC = (rs1 == rs2) ?PC + imm : PC + 4imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 BNEPC = (rs1 != rs2) ?PC + imm : PC + 4imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 BLTPC = (rs1s < rs2 s) ?PC + imm : PC + 4imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 BGEPC = (rs1s rs2 s)?PC + imm : PC + 4imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 BLTUPC = (rs1u < rs2 u) ?PC + imm : PC + 4imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 BGEUPC = (rs1u rs2 u) ?PC + imm : PC + 4 U-type31 12 11 7 6 0imm[31:12] rd opcode Mnemonic Descriptionimm[31:12] rd 0010111 AUIPC rd = PC + immimm[31:12] rd 0110111 LUI rd = imm J-type31 12 11 7 6 0imm[20|10:1|11|19:12] rd opcode Mnemonic Descriptionimm[20|10:1|11|19:12] rd 1101111 JALrd = PC + 4PC = PC + immHomework Description Modulea. top_tb moduleb. top_tb is not a part of CPU, it is a file that controls all the programand verify the correctness of our CPU. The main features are as follows:send periodical signal CLK to CPU, set the initial value of IM, print thevalue of DM, end the program.You do not need to modify this module.c. top moduletop is the outmost module. It is responsible for connecting wiresbetween CPU, IM and DM.Here are the wires: instr_read represents the signal whether the instruction should beread in IM. instr_addr represents the instruction address in IM. instr_out represents the instruction send from IM . data_read represents the signal whether the data should be read inDM. data_write represents the signal whether the data should be wrotein DM. data_addr represents the data address in DM. data_in represents the data which will be wrote into DM . data_out represents the data send from DM .You do not need to modify this module.d. SRAM moduleSRAM is the abbreviation of Instruction Memory (or DataMemory). This module saves all the instructions (or data) and sendinstruction (or data) to CPU according to request.A0 A1Mem[A1]DataclkaddrreadwriteDIDOWrite & Read Read IdleMem[A0] DataYou do not need to modify this modulee. CPU moduleCPU is responsible for connecting wires between modules,please design a single-cycle RISC-V CPU by yourself. You can writeother modules in other files if you need, but remember to include thosefiles in CPU.v.You should modify this module.

Reference Block Diagram Register FileRegister ABI Name Description Saverx0x1x2x3x4x5x6 7x8x9x10 11×12 17×18 27×28 31zeroraspgptpt0t1 2s0/fps1a0 1a2 7s2 11t3 6Hard-wired zeroReturn addressStack pointerGlobal pointerThread pointerTemporary / alternate link registerTemporariesSaved register / frame pointerSaved registerFunction arguments / return valuesFunction argumentsSaved registersTemporatiesCallerCalleeCallerCallerCalleeCalleeCallerCallerCalleeCaller Test Instructiona. Memory layout.text.rodata.fini.initUnmapped_test.bss.data.sdata.sbss.stacksetup.Smain.SStack dataUnmapped0x000000000x000080000x00010000DMIMFigure 2. Memory layout .text: Store instruction code. .init & .fini: Store instruction code for entering & leaving theprocess. .rodata: Store constant global variable. .bss & .sbss: Store uninitiated global variable or global variableinitiated as zero. .data & .sdata: Store global variable initiated as non-zero .stack: Store local variablesb. setup.SThis program start at PC = 0, execute function as followings:1. Reset register file2. Initial stack pointer and sections3. Call main function4. Wait main function return, then terminate programc. main.SThis program start after setup.S, it will verify all RISC-Vinstructions (31 instructions).d. main0.hex & main1.hex & main2.hex & main3.hexUsing the cross compiler of RISC-V to compile test program, andwrite result in verilog format. So you do not need to compile aboveprogram again. Simulation ResultRegister Value (hex)DM[ 0]DM[ 1]DM[ 2]DM[ 3]DM[ 4]DM[ 5]DM[ 6]DM[ 7]DM[ 8]DM[ 9]fffffff0fffffff800000008000000010000000178787878000091a200000003fefcfefd10305070DM[ 10]DM[ 11]DM[ 12]DM[ 13]DM[ 14]DM[ 15]DM[ 16]DM[ 17]DM[ 18]DM[ 19]DM[ 20]DM[ 21]DM[ 22]DM[ 23]DM[ 24]DM[ 25]DM[ 26]DM[ 27]DM[ 28]DM[ 29]DM[ 30]DM[ 31]DM[ 32]DM[ 33]DM[ 34]DM[ 35]DM[ 36]DM[ 37]DM[ 38]DM[ 39]DM[ 40]DM[ 41]DM[ 42]DM[ 43]DM[ 44]DM[ 45]cccccccc00000d9d0000000400000003000001a600000ec62468b7a85dbf9f0000012b38fa2817b7ff000000000f00000000f00000000f00000000f00000000f000f0000000f0000000f0000000f0000000f00000000000f000000f000000f00000f0003000f0002000f0001fffff000fffff000fffff000fffff000fffff000fffff0001357a04013578000fffff004Homework Requirements1. Complete the Single cycle CPU that can execute all instructions from theRISC-V ISA section.2. Verify your CPU with the benchmark and take a snapshot (e.g. Figure 3)Figure 3. Snapshot of correct simulationa. Using waveform to verify the execute results.b. Please annotate the waveform3. Finish the Project Report.a. Complete the project report. The report template is provided.ImportantWhen you upload your file, please make sure you havesatisfied all the homework requirements, including the Filehierarchy, Requirement file and Report format.If you have any questions, please contact us.