Objective

The objective of this lab is to design an Arithmetic and Logic Unit (ALU) using VHDL. In particular, in this lab the ALU should be defined using the behavioral model. The ALU component is illustrated in Figure 1, and the specification for the instructions to implement are included in Table 1.

Carryin

Figure 1: ALU Unit to be developed in this Lab project

Table 1: ALU control Lines and corresponding ALU Operations

Lab Design

Write a VHDL code to design the ALU component which performs the operations given in Table 1 for the given ALU control signals and two 32-bit inputs A and B. The result of the operation appears on 32-bit output port ALUout. The ALU also computes three flag bits Zero, Carryout, and Overflow.

Testing the Design

• Calculate the ALUout, Zero, Overflow, and Carryout values for the given inputs in Table 2.
• Write a test-bench to test your design for the given inputs of A, B, Carryin, and ALUCntl in Table 2 and compare the results with your calculated values.

Lab Report

Your report should include the following sections:

• Lab objective and your approach in designing the ALU unit
• Calculations of Table 2
• Conclusion