[SOLVED] Cda 4205l lab #8: single-cycle cpu implementation

Welcome to CDA 4205L Lab #8! The goal of this lab is to demonstrate an example implementation of a single-cycle CPU in Verilog HDL. Prelab This lab builds on the ALU and Control Unit design from Lab #7. You will be provided a near-complete single-cycle RISC-V CPU implemented in Verilog HDL. This implementation is almost capable of running code generated by your assembler from Lab #3 and #4 – but one critical component is missing – the instruction memory. Creating an instruction memory In Verilog module is done by first declaring a generic memory variable and loading the assembler output (machine code) into it. The Verilog command $readmemb(, ) will read the data from and load it into . This is for simulation purposes only, so you can simply place the command in an initial block. If your instructions are written in hex, the command $readmemh() will work the same way. Lab Setup 1. Download the Vivado project files from Canvas. 2. Open the file instr_mem.v. This file contains a template for a memory module. 3. Declaring a memory is very similar to declaring a register (reg) variable. The main difference is that you must specify the depth as well as the width. In this case, there are already parameters as part of the module definition (DATA_WIDTH, ADDRESS_WIDTH, NUM_MEM_CELLS) that are preinitialized. Note that, while these values are defaults, when you instantiate a new InstMem module in the top-level, you can override them to be whatever size you need. This lets you reuse the module in different designs without extra work. Declare a memory using the syntax reg [DATA_WIDTH – 1 : 0] inst_mem[0 : NUM_MEM_CELLS – 1] 4. Next, initialize the memory in an initial block. Use the $readmemb() directive. This command takes two parameters, the memory file name, and the memory variable you created in step 3. Note that referencing a macro definition requires prepending with `. 5. Finally, because this memory is part of a single-cycle implementation, data is not read synchronously. Hence, we do not use a clock; instead, it is a continuous assignment statement in the form assign data = inst_mem[