In final project, you are asked to design a pipelined MIPS processor (synchronous active low reset) with instruction cache and data cache. This processor should at least support the instruction set defined in Table 1. The instruction set is referenced from Appendix A of [1], and we encourage you read it in detail.

The whole module hierarchy is shown in Figure 1. And the processor architecture is shown in Figure 2 referenced from Chapter 4 of [1]. As you see, the processor architecture is modified from single-cycle architecture of our HW3. Your design should follow this 5-stage pipelined architecture. You need to modify several parts to fit our specifications. For example, you need to add the path for J-type instructions.

Also, you should solve the hazards by adding some circuits. There are 3 hazard categories should be properly handled in your pipelined processor:

• Structure hazard
• Data hazard
• Branch hazard

Although all of these hazards can be solved by insert NOP manually or automatically in your test program, we ask you to implement data forwarding unit and pipeline stall unit to solve these hazards.

Figure 1. Module Hierarchy

Figure 2. Simplified Pipeline Architecture of MIPS.

2. Cache and Memory Interface

The instruction memory and data memory will not be contained in your design. The memory interface is left as module I/O. You have to use the provided slow memory model. Do not synthesize the slow memory.

The cache units are suggested to have the same block number (8) and block size (4) as those in HW4. Besides, we do not restrict the replacement policy and writing policy of the cache design. You are encouraged to optimize the cache units to fit your MIPS design.

3. Synthesis Notes

You should synthesize your design using TSMC 0.13 cell library, and the relevant files, e.g. .synopsys_dc.setup, can be copied from previous HW or use the attached file. The design constraints are specified in CHIP_syn.sdc. Note that the pipelined MIPS, instruction cache, and data cache are included in the CHIP.v. They should be synthesized together.

The post-synthesis simulation is required and all involved Verilog files should be all modeled by gate-level. Note that the maximum clock frequency must be verified by post-synthesis gate-level simulation. And you are recommended to buffer the input signal to avoid timing violation.