[SOLVED] ECE-GY 9423 Design and Analysis of Communication Circuits and Components Fall 2024 Homework

ECE-GY 9423: Design and Analysis of Communication Circuits and Components (Fall 2024)

Homework # 5 (Due on Thursday, November 7th, 2024 before 11:59 pm EST.)

HW: All your calculations should have parametric expressions (wherever possible) and numerical answers (wherever required).

Reading assignment: Read through Chapter 4 and 5 of Razavi’s Analog CMOS design

Problem 1 (Differential Stage Large Signal Analysis):

For the differential pair stage with resistive load of RD, our goal is to plot the (vout  =  vout1  −  vout2 as a function of differential input (∆v  =  v1  −   v2) and evaluate the impact of design variables such as transistor dimensions, and the tail current source on the performance.

a)  Assuming ∆v   changing  from −vDD to vDD (VDD>>VTH),  plot the Vout(t) versus ∆v and determine the opera rating regions of both transistors during the transitions. For simplicity, ignore the channel length modulation and the body effect. How much voltage difference if needed to steer the current to one side? (10pts)

b)  If you were to use this stage as an amplifier, what region of the Vout-∆v curve is desired and why? Write down the expression for the effective transconductance of this stage from ΔID+Δv and plot the GM  versus -∆v. (10pts)

c)  Now, let’s evaluate the impact of the transistor dimensions and tail current source on diff. pair. Plot ID1  − ID2  versus -∆v when transistors ’ width is quadrupled and comment on the impact  on  the  linear  range  and  the  small  signal  gain.  Repeat  the  process  when  the dimensions are intact but the tail current source is quadrupled. (15pts)

d)  In reality, no two components are exactly identical because of process mismatch and fabrication accuracy. Let’s consider an extreme case where M2  is sized as 2(W/L) while M1 is sized as (W/L). Assuming the DC level of vin1  and  vin2  are equal, calculate the small-signal gain. Hint: Due to the imbalance, there is no virtual ground in this case.

e)  Now  assume  RD1  and  RD2  have  a  small  mismatch  that  could  be   expressed  as ΔR (RD2 = RD1 +  ΔR). Assuming  (W/L)1,2 = 50/0.5 and RD = 2 kΩ  . Suppose RSS represents the output impedance of an NMOS current source with (W/L)SS  = 50/0.5 and a drain current of 1 mA. The input signal consists of Vin,DM  = 10 mVpp and Vin,CM  =  1.5 V + Vn(t), where Vn(t) denotes noise with a peak-to-peak amplitude of 100 mV. Assume that R/R = 0.5%. Calculate the output differential signal-to-noise ratio, defined as the signal amplitude divided by the noise amplitude. (15pts)

f)   Calculate the CMRR. (15pts)

Problem 2 (Small signal modeling):

Assuming that all the transistors in following are saturated and λ   = 0, calculate the small-signal differential voltage gain of each circuit. (Try to avoid writing KVL/KCL without making invalid assumptions in your modeling) (30pts)