[SOLVED] Ceng2010 lab 4: finite state machine

1. Implement the following Mealy Finite State Machine using VHDL. In the transitions below, for instance, 01/0 denoted that input
RESET=0, input INPUT=1, and output=0. [60 marks]a. Use switch sw0 as system INPUT
b. Use btnC button as the CLOCK signal to synchronize the whole machine by its rising edges. Since we are not using the
real CLOCK signal on the board, please avoid naming this CLOCK as “CLK” or “CLOCK” in the VHDL codes.c. Use btnD button to RESET the machine to S0 when pressed.
d. Use led0 to show the system outpute. Turn led5, led6, or led7 on when the system at State S0, S1, or S2 respectivelyf. Name the processes similar to the examples in the lecture notes, i.e. SYNC_PROC, OUTPUT_DECODE, and
NEXT_STATE_DECODE
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