[SOLVED] CS Sequential Circuits

Sequential Circuits
25

COMP273 McGill
26
a RS Latch
a D Latch
a D Flip flop a T Flip flop
Agenda

COMP273 McGill
27
Sequential Circuits a Combinatorialcircuitshavenomemory
Output is simply a function of inputs
a Sequentialcircuits}vo]v^eoo_
Combinatorial circuits + memory
The mechanism for remembering information (i.e., bits) inside the CPU and in the main memory.
How to remember things?
a Write it down
a Repeat it to yourself (sequential circuits style)

Latch
28

COMP273 McGill
29
a TwoinputsSandR
S = 1, set output to 1 R=1,resetoutput to0
S, R are both 0, hold the values
2Z ^2 Y2 Yn2 I2 I2 Q Q I2I21 0 I2I20 1
RS Latch

COMP273 McGill
30
RS Latch When S, R are both 1, invalid
a Problem:
2Z ^2 Y2 Yn2
I2 I2 Q Q I2I21 0 I2I20 1
I2 I2 invalid invalid

a Mechanismforsynchronizinginputsandoutputs. a Metronome
a Clock speed is in Gigahertz
Clocks
COMP273 McGill https://bestanimations.com/gifs/Black-And-White-Old-Metronome.html 31

a Recall that it takes time for combinatorial circuits to produce results.
a Wantresultsto
be finished before we store the result somewhere
COMP273 McGill
32
e.g., carry ripple in adder
http://goo.gl /n3fKv
Clocks

a WhenC=0,holdvaluesofQandQ
a WhenC=1,D=1,thensetQ=1,Q=0
a WhenC=1,D=0,thenresetQ=0,Q=1 a Impossible for R and S to be both 1
D Latch
COMP273 McGill 34

a Still not good enough
Data passes freely though the circuit while C =1.
COMP273 McGill
35
Mightwantdothingslikex:=x+27
D Latch
What happens if we combine an array of D latches with a combinatorial adder circuit?

Flip-flop
36

D flip-flop
a TwoDlatches.Oneforreadingandoneforwriting
a Mechanism prevents data from being read/write at the same time
a By putting an inverter, change when the falling edge is triggered
COMP273 McGill 37

COMP273 McGill
38
a WhenC=1
write D into the first D latch Q does not change
a WhenC=0
D flip-flop
Stop writing D into the first D-latch.
The D value from the first D-latch is written into the second D-latch

COMP273 McGill
39
a a
D flip-flop Setup and Hold
Setup time: Input must be stable before the falling clock edge
Hold time: Input must also be stable after clock edge Hold times typically very small, or zero

Toggle Flip Flop
a ,}}lY[ao}Uvo}l}uetoggle
COMP273 McGill 40

a RS Latches a D Latch
a D Flip flop a T Flip flop
Review and more information
a Textbook: Appendix B.7 and B.8 of 5th and 6th edition a Nexttopic:Registers(usesequentialcircuits)
COMP273 McGill 41