[SOLVED] CS cache Registers and Memory

Registers and Memory
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Registers
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Register
a Registers are circuits inside of the processor
a Registers used extensively throughout the datapath
e.g. adding two numbers. The numbers are temporary stored in the registers and becomes the inputs of ALU

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(General) Register
a General purpose: Store a multibit datum, e.g., byte or word
a Can implement with an array of D flip-flops
4-bit General Register

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a Shifts the stored bits on each clock
a Can be designed to shift left or right
Shift Register
a What can this be useful for?
Multiplication or division by two
Conversion between serial and parallel interfaces

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a Thecounterfortheprocessor
a AsetofTflipflop
Count Register
a Countuporcountdown,butwhen?
Count up toggled on rising-edge
Count down toggled on falling-edge
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Register Files
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a A collection of registers
a Can read two registers
a Canwriteoneregister
a Write triggered by clock (blue)
a How many bits on different inputs?
Register File
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a Use multiplexor to select which registers to read
Register File Reading
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a Combinedecoderwith clock using AND to store the write data
Register File Writing
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Register File with ALU
Instruction
ALU

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RAM Size 16 GB 14
SRAM
static random-access uu}a2
DRAM
Dynamic random-access memory
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Memory
Specification of Dell G5 Gaming PC
Processor Type 10th Generation Intel Core i7-10700 Processor Speed 2.90 GHz
Processor Cores 8
Processor Cache 16 MB Intel Smart Cache

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SRAM Multiplexor
a SRAM is HUGE and cannot be built like register files
The multiplexor grows with the number of memory locations
Giant OR is more realistically implemented with a tree of OR gates

SRAM Multiplexor a Instead,themultiplexorforSRAMis
Data Enable Out 010 111 x0Z
implemented with tri-state buffer
a Tri-state buffer
Select = 1, output = data
Select = 0, output = high impedance state a Effectively disconnected
a Denoted Z in truth table
a Only one out is active (or short circuit) COMP273 McGill
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SRAM Multiplexor
Avoid AND array and OR tree with an array of Tri-State buffers
Need carefully design the select signal to avoid short circuits
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YYYXYYYXX
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a May still need a large decoder
a 1 megabit memory would need a
1048576 D Flipflops and Tri-state buffers
20 to 1,048,576 decoder!
D D
3-to-8 decoder
HUGE decoder with over one million outputs! 19
SRAM Decoder
20 AtA20 to
1048576
0 19 1,048,576 decoder
D D
D
1 bit output

YXX
YXX
YXX
YXX
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AtA 10
10 19 1024
A tA
09 1024
0 1 2 YXX1023
10
to 1024
D D D YXXD D D D YXXD D D D YXXD
decoder
10
to 1024
decoder
SRAM Decoder
multiplexor
1048576 D Flipflops and Tri-state buffers Organized in 1024 by 1024 grid
D D D YXXD
Organizing memory in rectangular arrays and use two decoders
20
1 bit output

SRAM Decoder
a How much can we save from 1MB memory a A linear array
One 20 to 1048576 decoder for all address lines
a A rectangular array
One 10 to 1024 decoder for the upper address lines One 10 to 1024 decoder for the lower address lines
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Multi-bit Access
Multiple memories next to each other. Decoding can be reused!
Example: 4M x 8 bits. Each bit is a 4096 by 1024 array

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Basic 42 SRAM
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Multi-bit Access

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a a
Data is stored in D-Latch 4-6 transistors per bit.
a Data is stored in capacitor a Uses 1 transistor per bit.
a Much denser and cheaper.
SRAM
DRAM
DRAM vs SRAM

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SRAM
DRAM
a Data is stored if not overwritten and power is on
a
a
a SLOW
a Fixed access time
a Fast and used for caches
DRAM vs SRAM
Capacitor charge
is not permanent
Refresh consumes 1% to 2% of active cycle

a Registers
Data registers
Count registers Shift registers
a Memory SRAM
DRAM a Textbook
Review
B8, B9 of 5th and 6th edition, C7-C10 of 4th edition
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