[SOLVED] Midterm 2

Midterm 2

Create a circuit this is capable of doing division between two 5 bit unsigned integer numbers.

Remember that given a fraction
A
B

, A is called the dividend and B is called the divisor. The result of

the division is called the quotient. Your division circuit should be implemented using sequential logic
and should complete the division within 6 clock cycles of receiving its input.

Restrictions

You MAY NOT USE: RAM, ROM, or the Divider.
You may only use 1 Adder/Subtractor

You cannot create more by using combinational logic
You must implement a sequential circuit

Combinational solutions will receive 0 credit.
You cannot implement the combinational solution presented in the book and then just place

the result in a register

Inputs
Name Width Description

Dividend 5 The dividend. This input will
only be valid during the first
clock tick that Divide is 1. This
means you will have to store the
Dividend.

Divisor 5 The divisor. This input will only
be valid during the first clock
tick that Divide is 1. This means
you will have to store the
Divisor.

Divide 1 When divide is 1 your process
for division of the dividend by
the divisor should start. Once
your process begins it should
ignore Divide until the division
is complete. When divide is 0
your outputs should remain the
same.

Outputs
Name Width Description

Ready 1 1 if your circuit is ready to
perform the next division and 0
if it is currently doing division.
When Ready is 1 it also signifies
that you have completed your
division.

Quotient 5 The quotient. On start up this
value should be 0. If after
completing the division, divide is
0 then this value should continue
to hold the quotient of the most
recent division. While doing
division this value is a dont care.

Remainder 5 The remainder. If after
completing the division, divide is
0 then this value should continue
to hold the remainder of the most
recent division. While doing
division this value is a dont care.

Hints
1. A program that divides 32 bit numbers has been provided to you. This will help you to think

about how to implement it in hardware. Try to keep in mind the limitations of the hardware and
the fact that your solution must complete within 6 clock cycles.
1. Completing within 6 clock basically means that you cant have a for/while loop that runs for

more than 6 iterations.
2. When converting to hardware all instructions within a block of code must be completed in

parallel.
3. Thank about how to translate the structures into hardware

1. How should a variable be represented in hardware? An if statement? A Loop?
2. Think about how to solve this problem similar to the way we solved the problem of designing a

CPU.
1. Build your data path first and once it is done figure out the control signals.

3. Components I used but not their counts: Register, Shift Register, Comparator, Mux, basic logic
gates, bit shifter, bit extender, Subtractor, Counter, Constant, Ground, and Splitter.

Midterm 2
Restrictions