[SOLVED] CS CSCI-UA.0201-003

CSCI-UA.0201-003
Computer Systems Organization
Exam 2 Fall 2018 (time: 60 minutes)
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If you perceive any ambiguity in any of the questions, state your assumptions clearly.
Questions vary in difficulty; it is strongly recommended that you do not spend too much time
on any one question.
The exam consists of 5 pages, 5 questions, and a total of 50 points. Last paper is left
intentionally blank, for you to use if you want.
You answer on the question sheet.
1. (6 points) Circle the correct answer among the choices given. If you circle more than one answer, you will lose the grade of the corresponding question.
(A) When you have an unsigned int in your C program, the compiler will use what type of instruction when it generates the x86 assembly?
1. movb 2. movl 3. movq 4. movw
(B) If we have three processes currently being executed in the system, how many heaps does the system currently have?
1. one 2. two 3. three 4.four
(C) The dynamic memory allocator does not need to keep track of allocated blocks in the heap. This statement is:
1. True 2. False 3. Depends on programming language
(D) If a process has a 1MB heap and another process has 100KB heap. Assume the dynamic memory allocator used by both processes uses implicit list. Which statement of the following is true?
1. The memory allocator for the 1MB heap will be slower.
2. The memory allocator for the 100KB heap will be slower.
3. We cannot tell for sure.
4. Depends on the original programming language used in each process.
(E) The TLB is accessed with:
1. virtual address 2. physical address 3. depends on the OS 4. depends on the compiler
(F) If we keep the total cache size fixed, and increase the associativity. The number of sets 1. increases 2. decreases 3. stays fixed
4. depends on whether we will change block size or not.

2. Suppose we have a cache memory of 32 blocks. The address length is 32 bits. address is divided as follows:
* 5 bits for the offset * 4 bits for the set
(a) [3 points] What is the associativity of that cache?
Associativity = total number of blocks in the cache / number of sets #sets = 24 = 16
Associativity = 32/16 = 2
(b) [3 points] What is the block size? block size = 2#bits in offset = 25 = 32 bytes
(c) [3 points] What is the total cache size in bytes [leave it in the form of 2x]?
total cache size = total number of blocks * block size = 32 * 25 = 210 bytes
(d) [3 points] Suppose the main memory access time is 200 cycles and the cache has an access type of 2 cycles. The cache hit rate is 80%. What is the average memory access time?
average memory access time = p*m + (1-p)*(M+m) p = 0.8 m = 2, M= 200
avg mem access time = 0.8*2 + 0.2*202 = 1.6 +40.4 = 42 cycles
(e) [3 points] Based on what you calculated in (d) above, did the system benefit from having
a cache or not? Justify.
Yes, the system benefit from having a cache, because now the avg memory access time is 42 < 200 cycles that would have been if there was no cache.3. [6 points] Given the following x86_64 assembly code and its corresponding C code, fill-in the blanks in the corresponding C code. Also on the far right, fill in the correspondence between each register and its corresponding variable in C.cmpl %esi, %edisubl leal ret(%rdi,%rsi), %eax%edi, %esi 10(%rsi), %eaxint square(int a, int b ) { int sum = ___10___;if( a > b)
sum = ___a + b__;
_sum += (a-b)_;
return sum; }
edi a esi b eax sum
a. [2 points] Even though all the variables are int, in the above example, and hence we use the e- version of registers (e.g. eax, edi, etc) yet, there two leal instructions above use the r-version of the registers in the source part, why?
Because the source part of lea is an address and for all current 64-bit machines, all addresses are 64 bits. Therefore, compiler must use 64-bit version of the registers.
b. [1 point] How many times does the instruction leal 10(%rsi), %eax access memory? 0 times

4. For the following piece of code:
void par() {
if (fork() != 0) {
fork(); printf(3); }
else printf(4);
int main() { printf(1);
par(); printf(2); exit(0);
a. [2 points] How many times will the digit 2 be printed? 3 times
b. [2 points] How many processes exist in the system just before any process exits? three processes
c. [4 points] Based on your answer in part b above, and assuming the OS uses one-level page table and one-level cache, indicate how many of each of the following exist in the system just before any process exits.
caches: 1 TLB: 1
Page Table: 3

5. For each of the following problems, write one x86 instruction that does the action specified in the corresponding problem.
(a) [3 points] Assume the unsigned long x is stored in register rax. Put 9x in register rbx without using multiplication operation.
leaq (%rax, %rax, 8), %rax
(b) [3 points] Set the zero flag to 1
Any instruction that has a zero as a result will do it. Example:
subq %rax, %rax
(c) [3 points] Set the least significant bit (i.e. right most) of rax to 1.
orq $1, %rax
(d) [3 points] Set the least significant bit and the most significant bit of eax to 0
andl 0x80000001, %eax

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