High Performance Computer
Architecture Revision Exercise #1
Time allowed: 1 hour (i.e. for your own revision and practice) Full score : 50 marks
o This review exercise will be useful for you to revise the concepts covered in this course, esp. before examination. It is solely for your OWN REVISION AND THUS NO NEED TO SUBMIT the answers to me.
o Trytoattempteachquestionandthenreviewthesuggestedanswersafterwards.
o The whole exercise consists of 5 pages. Check it out yourself.
o Time your handling of this exercise. You are advised to leave the last 5 minute of 1 hour to check your answer.
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Question 1. (25 marks)
True or False. Choose the BEST answer. (2.5 mark each)
(a) Pipeline rate is limited by the slowest pipeline stage. T F
(b) Data hazards occur when an instruction depends on the result of an already completed
instruction that is not existed in the pipeline anymore.
(c) Structural hazards arise in contention of resources in the computers.
(d) The time required to “fill” and “drain” a pipeline increases the speedup.
(e) VLIW architectures need heavy support from the compiler.
(f) Scoreboard keeps track of dependencies between instructions that have already been issued.
TF
(g) Usually recompilation of source is needed for superscalar architectures. T F
(h) Loop unrolling always requires the same set of registers to execute the original loop. TF
(i) Clock rate reduction can help reducing power consumption. T F
(j) Structural hazards arise in contention of different resources by various instructions. TF
Answer:
T F T F T F T F
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Question 2. (15 marks)
The figure above shows the status of the scoreboard at the end of the 19th cycle for the instruction sequence listed at the upper left corner.
(a) (7 marks) As can be seen, the ADDD instruction has finished the EXEC stage in cycle 16 already. Why the ADDD instruction cannot proceed to the WRITE RESULT stage?
Answer:
(b) (9 marks) How does the Tomasulo architecture tackles the 3 different kinds of data hazards? Answer:
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Question 3. (10 marks)
I
F D Ex1 Ex2 Ex3 Ex4 Ex5 W
The above figure shows a pipeline with one fetch stage, one decode stage, multiple execution stages (which include memory access), and a single write-back stage. The functions performed by the stages are as follows:
• • •
•
•
• • •
F: fetch next instruction
D: decode stage
EX1:
– integer operations, or
– address computations (for LOAD/STORE), or – first stage of: ADDF, MULTF, DIVF
EX2:
– first stage of: LOAD/STORE (memory access), or – last stage of: DIVF, or
– second stage of: ADDF, MULTF
EX3:
– last stage of: LOAD/STORE (memory access), ADDF, or – third stage of: MULTF
EX4: fourth stage of MULTF EX5: last stage of MULTF W: writeback stage
The “backward” arrows are the bypass paths, each of which indicates that the result (output) of a stage for certain instructions can be forwarded to some earlier stages in subsequent instructions in the pipeline. For example, for an integer (I) instruction, the result of execution from the output of the EX1 stage (which can also be obtained in all later execution stages), can be forwarded to the EX1 stage in subsequent instructions. On the bypass paths, I denotes integer operations, D denotes DIVF, A denotes ADDF, Ld denotes LOAD, and M denotes MULTF.
(a) (5 marks) How many extra instructions are required between each of the following pairs of instructions to avoid stalls, assuming that the second instruction uses a value from the result of the first?
(i) DIVF and STORE
I,D
I,D,Ld,A,M
I,D,Ld,A I,D,Ld,A
D
Ld,A
M
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(ii) LOAD and MULTF
(iii) Two integer instructions
(iv) MULTF and ADDF
(v) ADDF and DIVF
Solution:
(b) (5 marks) In the traditional 5-stage pipeline, if a load into a register followed by an immediate store of that register to memory would not require any stall, i.e., the following pair of instruction could run without stall:
Is this still true for the above 8-stage pipeline? Explain. Answer :
lw $r4, 0($r2) sw $r4, 0($r3)
****END OF REVISION EX. 1****
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