COMP122
COMP 122 Dr Jeff Drobman
drjeffsoftware.com/classroom.html
[email protected]
© Jeff Drobman 2016-2019
ASSEMBLY Programming/ISA
MIPS, RISC-V
website
email
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ISA Index
© Jeff Drobman 2016-2019
vComparativeàslide 3 vMIPS (I, MIPS32)àslide 15 vRISC-Vàslide 63
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ISA
Comparative
© Jeff Drobman 2016-2019
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Compare ISA’s
vDesktop CPU’s (Large) q Alpha
q MIPS
q PowerPC q PA-RISC qSPARC
vEmbedded CPU’s (small) q ARM
q Thumb q SuperH q M32R q MIPS-16
© Jeff Drobman 2016-2019
MIPS vs. ARM Instructions COMP122 Hennessy & Patterson
© Jeff Drobman 2016-2019
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Desktop Instructions
Hennessy & Patterson
© Jeff Drobman 2016-2019
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Embedded Instructions
Hennessy & Patterson
© Jeff Drobman 2016-2019
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Embedded Instructions
Hennessy & Patterson
© Jeff Drobman 2016-2019
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Addressing Modes
© Jeff Drobman 2016-2019
Hennessy & Patterson
Desktop
Embedded
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Address Sign Extension
© Jeff Drobman 2016-2019
Hennessy & Patterson
Desktop
Embedded
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MIPS vs ARM
© Jeff Drobman 2016-2019
Hennessy & Patterson
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MIPS vs ARM
© Jeff Drobman 2016-2019
Hennessy & Patterson
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MIPS vs ARM
© Jeff Drobman 2016-2019
Hennessy & Patterson
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MIPS vs ARM
© Jeff Drobman 2016-2019
Hennessy & Patterson
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ISA
MIPS
© Jeff Drobman 2016-2019
COMP122
MIPS
© Jeff Drobman 2016-2019
Wikipedia
MIPS
COMP122
MIPS ISA’s
1999
© Jeff Drobman 2016-2019
Wikipedia
MIPS
R6000
1989
R4000
1991
64-bit
Extensions
v Privilege states Ø Kernel
Ø Supervisor Ø User
Base ISA
1985
R2000àR3000
32-bit
COMP122
MIPS Cores
© Jeff Drobman 2016-2019
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MIPS ISA’s & Modules
© Jeff Drobman 2016-2019
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MIPS Core Details
© Jeff Drobman 2016-2019
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MIPS32 ISA
© Jeff Drobman 2016-2019
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MIPS I– Base (R2000) Org
© Jeff Drobman 2016-2019
Hennessy & Patterson
MIPS
CPU FPU
COMP122
Instruction Formats
© Jeff Drobman 2016-2019
Wikipedia
MIPS
q “shamt” ::= shift amount (5 bits)
q “funct” ::= function (opcode extension – 6 bits)
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Directives
Ø Special chars in “Strings”
© Jeff Drobman 2016-2019
Hennessy & Patterson
MIPS
Labels:
Memory segments
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Directives
© Jeff Drobman 2016-2019
Hennessy & Patterson
MIPS
COMP122
Directives
© Jeff Drobman 2016-2019
Hennessy & Patterson
MIPS
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GP Registers
© Jeff Drobman 2016-2019
Hennessy & Patterson
v $a(0:3) args
v $at, $k(0:1) reserved v $v(0:1) values
v $t(0-9) temp v$s(0:7) saved v$gp globalptr v$sp stackptr
v$fp frameptr v$ra returnaddr
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Address Formats
Hennessy & Patterson
© Jeff Drobman 2016-2019
($at)
+4
+4 ($at)
Label +4 Label +4 ($at)
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MIPS Assembly
© Jeff Drobman 2016-2019
MIPS
Lab 1
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ALU
MIPS I ISA
© Jeff Drobman 2016-2019
CPU
Wikipedia
CPU
Hennessy & Patterson
X*Y +A
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MIPS32 ISA
© Jeff Drobman 2016-2019
CPU
Shift
Wikipedia
Mult Div
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
COMP122
MIPS32 ISA
© Jeff Drobman 2016-2019
CPU
Hennessy & Patterson
COMP122
LOAD
MIPS I ISA
© Jeff Drobman 2016-2019
CPU
Wikipedia
STORE
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LOAD
MIPS32 ISA
© Jeff Drobman 2016-2019
CPU
Hennessy & Patterson
STORE
Ø Multiprocessing extensions
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Jump + Branch
MIPS I ISA
© Jeff Drobman 2016-2019
CPU
Wikipedia
COMP122
MIPS32 ISA
© Jeff Drobman 2016-2019
CPU
Hennessy & Patterson
CP1
Wikipedia
FP
System
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
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MIPS I ISA
© Jeff Drobman 2016-2019
CP0-1
Wikipedia
COMP122
MIPS32 ISA
© Jeff Drobman 2016-2019
Coprocessor 1
Hennessy & Patterson
FPU
COMP122
MIPS32 ISA
© Jeff Drobman 2016-2019
Coprocessor 1
Hennessy & Patterson
FPA
COMP122
MIPS32 ISA
© Jeff Drobman 2016-2019
Coprocessor 1
Hennessy & Patterson
FPU
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
Formats
Instruction Details
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
Add/Sub
Instruction Details
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
Mul/Div
Instruction Details
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
Load/Store
Instruction Details
COMP122
Load Pseudo Ops
© Jeff Drobman 2016-2019
COMP122
Load: lui vs. $gp
© Jeff Drobman 2016-2019
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MIPS I ISA
© Jeff Drobman 2016-2019
BR/Jump
Instruction Details
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
EPC
Instruction Details
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
FP Load/Store
Instruction Details
COMP122
MIPS I ISA
© Jeff Drobman 2016-2019
FP
Instruction Details
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Control CP0
© Jeff Drobman 2016-2019
Hennessy & Patterson
Exception handler
Interrupts(8)
IE User/system
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Exceptions (EPC)
Hennessy & Patterson
© Jeff Drobman 2016-2019
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Opcode Map
© Jeff Drobman 2016-2019
Hennessy & Patterson
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Opcode Map
© Jeff Drobman 2016-2019
Hennessy & Patterson
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MIPS II-III ISA
© Jeff Drobman 2016-2019
CPU
Wikipedia
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MIPS III ISA
© Jeff Drobman 2016-2019
CPU
Wikipedia
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MIPS32 ISA
vTraps
© Jeff Drobman 2016-2019
CPU
Hennessy & Patterson
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MIPS32 ISA
© Jeff Drobman 2016-2019
CPU
Hennessy & Patterson
COMP122
MIPS32 ISA
© Jeff Drobman 2016-2019
CPU
Hennessy & Patterson
COMP122
MIPS32 ISA
© Jeff Drobman 2016-2019
Coprocessor 2
Hennessy & Patterson
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ISA
RISC-V
© Jeff Drobman 2016-2019
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RISC-V
© Jeff Drobman 2016-2019
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RISC-V
© Jeff Drobman 2016-2019
XLEN = 32/64
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RISC-V
© Jeff Drobman 2016-2019
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RISC-V
© Jeff Drobman 2016-2019
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RISC-V
ALU
© Jeff Drobman 2016-2019
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RISC-V
IMM
© Jeff Drobman 2016-2019
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RISC-V
BR
© Jeff Drobman 2016-2019
COMP122
JMP
RISC-V
© Jeff Drobman 2016-2019
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RISC-V
NOP
© Jeff Drobman 2016-2019
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RISC-V
© Jeff Drobman 2016-2019
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