POLLING
Copyright William D. Richard, Ph.D. November 12, 2019
The ability for a processor to fetch and execute code from memory is essential to any application, but useful applications need to interact with the external world to get data to process, to output processed data, to display graphics on monitor screens, etc. The non-memory portion of a computer system is called the Input/Output sub-system, or more commonly the I/O system. In CSE 362M, you will study advanced, high-speed I/O concepts like interrupt-driven I/O and Direct Memory Access (DMA), but first you need to understand the most basic of methods for implementing I/O: Polling.
The concept of polling is that, in software, the CPU system monitors the status of an input from an external device and then does something based on that input changing. Here, in lab 3, the ¡°external device¡± is a set of five (5) pushbuttons implemented inside the module called ¡°buttons¡± attached to the system address and data buses. The block diagram of the buttons subsystem for lab 3 is shown in the figure below.
READ.H
Looking at the decode logic, we see that the buttons subsystem is mapped to a single 32-bit word in the memory space of the CPU. In binary, the address decoded is ¡°11111111111111111111111111111100¡± expressed as a VHDL STD_LOGIC_VECTOR (the bottom two bits are actually don¡¯t cares). In decimal, this value is -4. When I/O devices are mapped to memory addresses, we say we are using ¡°memory mapped I/O.¡± Note: You cannot store a program at this location like you would to a normal memory location populated by RAM.
Looking ¡°inside¡± the buttons VHDL module, one finds that reading from the buttons subsystem returns the status of the five (5) pushbuttons in the bottom five (5) bits of the 32-bit word. By ¡°polling¡± the buttons, your assembly application can determine when to move, and in which direction, the drawing ¡°stylus¡± for your electronic Etch A Sketch.
To eliminate problems with metastability, the asynchronous external signals from the physical pushbuttons are synchronized using back-to-back flip-flops implied by the VHDL below.
RESET_L_SYNC
TIMER
D<31..0>
30
A<31..2> READ.H
BUTTONS_CE.L
5
CLK
— Buttons
— Copyright William D. Richard, Ph.D.
— November 11, 2019
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
ENTITY buttons IS
PORT (clk
END buttons ;
ARCHITECTURE foo OF buttons IS
SIGNAL f_tmp: STD_LOGIC_VECTOR(31 DOWNTO 0) ;
SIGNAL f_sync : STD_LOGIC_VECTOR(31 DOWNTO 0) ;
BEGIN
syncprocess:PROCESS(clk)
begin
IF (Clk = ‘1’ AND Clk’event) THEN
IF (reset_l = ‘0’) THEN
f_tmp<= “00000000000000000000000000000000” ;f_sync <= “00000000000000000000000000000000” ;ELSEf_tmp <= “000000000000000000000000000” & btnc & btnd & btnu & btnl & btnr ; f_sync <= f_tmp ; END IF;END IF; END PROCESS syncprocess ; readprocess:PROCESS(ce_l,oe_l,f_sync) beginIF (ce_l = ‘0’ AND oe_l = ‘0’) THEN d <= f_sync ;else d <= (OTHERS => ‘Z’) ;
END IF;
END PROCESS readprocess ;
END foo ;
reset_l
d
ce_l
oe_l :IN btnr :IN btnl :IN btnu :IN btnd :IN btnc :IN
: IN STD_LOGIC ;
:IN STD_LOGIC ;
: INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC) ;
:IN
Example RSRC assembly code to implement the polling required for lab 3 is shown below. TOP and BTN are ¡°labels¡± that you should mentally equate with memory addresses. The comments in the code provide an example of how you should comment your assembly code for your lab 3 solution in order to receive full credit.
.org 0
la r29,BTN
la r28,TOP
TOP: ld r4,0(r29) andi r5,r4,31
brzr r28,r5
nop
stop
.org -4 BTN: .dw 1
; r29 holds the button module address
; r28 holds the polling loop address
; Read the status of all the buttons
; Test for one or more button presses
; Keep polling until button pressed
; A button was pressed: Do something!
Inspection of the assembly code above reveals that polling is not really hard to implement: The program simply loops, continually reading the buttons, until one or more of the bits read from the buttons module changes from ¡®0¡¯ to ¡®1¡¯.
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