CPU Instructions
CS 154: Computer Architecture Lecture #4
Winter 2020
Ziad Matni, Ph.D.
Dept. of Computer Science, UCSB
Administrative
Lab 01 due today!
Lab 02 description will be out soon!
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Lecture Outline
Instruction Set Architectures (ISA) MIPS instruction formats
Refresher on some other MIPS instructions Reference material from CS64 Ill be going over this a little fast
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Other Factors to CPU Performance:
Power Consumption
Market trends DEMAND that power consumption of CPUs keep decreasing.
BUT Power and Performance DONT always go together Power = Capacitive Load x Voltage2 x Clock Frequency
So:
Decreasing Voltage helps to get lower power, but it can make individual
logic go slower!
Increasing clock frequency helps performance, but increases power!
Its a dilemma that has contributed to Moores Law plateau
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Other Factors to CPU Performance:
Multiple Processors
Multicore microprocessors
More than one processor per chip
Requires explicitly parallel programming
Compare with instruction level parallelism
Hardware executes multiple instructions at once Hidden from the programmer
Hard to do
Programming for performance
Load balancing
Optimizing communication and synchronization
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Pitfalls: Amdahls Law
Improving an aspect of a computer and expecting a proportional
Your benchmark time is 100, 80 of which comes from a part of the CPU that you want to improve by a factor of n, so:
improvement in overall performance
Timproved = (80 / n) + 20
If you wanted to improve your overall T by a factor of 2
(i.e. drop total from 100 to 50), then youd need to make n = 2.7 because 50 = (80 / 2.7) + 20 ok
Keep that up! Lets go for a factor of n = 5, so drop total from 100 to 20:
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i.e. 20 ?= (80 / 5) + 20
uh cant do thatL
Pitfalls: Idle Power
Simply put:
CPUs will still draw disproportionate power when idling.
Example, even when operating at 10% load,
the i7 will draw 47% of the power
Becomes a problem when dealing with large scale implementations, like data centers (Google, Facebook, Amazon, etc)
Design challenge: design processors to draw power more proportional to load (requires Physics-level approach, tho)
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Pitfall: MIPS as a Performance Metric
Note: Were NOT talking about MIPS the processor type!!!!
MIPS (millions of instructions per second) is a popular performance metric, HOWEVER
Doesnt account for
Differences in ISAs between computers
(some ISAs may be more efficient than others) Differences in complexity between instructions (weighted CPIs)
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Instruction Set Architecture (ISA)
The contract between software and hardware (hence, its an abstract model of a computer!)
Typically described with:
programmer-visible states (i.e. registers + memory) the semantics/syntax of the instructions
Examples abound in your MIPS Reference Card!
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Instruction Set Architecture (ISA)
Many implementations possible for a given ISA
Most microprocessor families have their own ISA
Some can be shared across families (b/c theyre popular)
Example: AMD and Intel processors both run the x86-64 ISA (orig. Intel). Some of the same ISAs can be customized
Many cellphones use the ARM ISA with specific implementations from many different companies including
Apple, Qualcomm, Samsung, Huawei, etc.
Well be using the MIPS ISA in this class.
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Classification of ISAs
By architectural complexity*
Intel, AMD (x86)
ARM, MIPS
GPUs (AMD, Nvidia) Intel/HP (IA-86)
CISC
RISC RISC EPIC
CISC vs RISC:
Higher instruction complexity (and CPI)
More transistors
Higher power
Commercial computers
vs. embedded computers
CISC (complex instruction set computer) and RISC (reduced instruction set computer)
* Most popular distinction in commercial CPUs
By instruction-level parallelism
VLIW (very long instruction word) and
EPIC (explicitly parallel instruction computing) By extreme simplification of instructions
MISC (minimal instruction set computer) and OISC (one instruction set computer)
EPIC/VLIW:
Less commercial than CISC/RISC
Server/supercomputer use mostly
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MISC/OISC:
Little to no parallelism
Mostly in research
The MIPS ISA
Developed at Stanford then commercialized by MIPS Technologies, created/led by John Hennessey
Stanford CS prof, President (2000-16), author of our textbook Started multiple important SV companies,
current Chair of Alphabet, Inc.
Hennessey and Patterson won the 2017 Turing Award for their work in developing RISC architecture
MIPS still has a large share of embedded core market
Consumer electronics, storage peripherals, cameras, printers,
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Code on MIPS
x = 5;
y = 7;
z = x + y;
Original
MIPS
li $t0, 5
li $t1, 7
add $t3, $t0, $t1
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Available Registers in MIPS
32 registers in all
Refer to your
MIPS Reference Card
Bring it to class from now on
Copy on main webpage
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Used for data
MIPS Instruction Formats
Each instruction is represented with 32 bits
There are three different instruction formats: R, I, J These allow for instructions to take on different roles
R-Format is used when its all about registers
I-Format is used when you involve (immediate) numbers
J-Format is used when you do code jumping
(i.e. branching)
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Since all instructions are 32-bits, then they each occupy 4 Bytes of memory. Remember: Memory is addressed in Bytes.
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Talking to the OS
We are going to be running on MIPS emulator called SPIM Optionally, through a program called QtSPIM (GUI based)
What is an emulator?
MIPS features a syscall instruction, which triggers a software interrupt, or exception
Outside of an emulator (i.e. in the real world), these instructions pause the program and tell the OS to go do something with I/O
Inside the emulator, it tells the emulator to go emulate something with I/O
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syscall (for spim use)
The OS/emulator has access to the CPU registers
So we have the OS/emulators attention, but how does it know what we want?
We put special values (codes) in the registers to indicate what we want
These are codes that cant be used for anything else, so theyre understood to be just for syscall
So is there a code book????
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Yes! All CPUs come with manuals. For us, we have the MIPS Ref. Card
MIPS System Services
stdout
stdin
File I/O
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System call code: placed in $v0 Argument: placed in $a0
Bring out your MIPS Reference Cards!
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NOTE THE FOLLOWING:
1. Instruction Format Types: R vs I vs J
2. OPCODE/FUNCT (Hex)
3. Instruction formats: Where the actual bits go
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NOTE THE FOLLOWING:
1. Pseudo-Instructions There are more of
these, but in this class, you are ONLY allowed to use these + la
2. Registers and their numbers
3. Registers and their uses
4. Registers and their calling convention
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NOTE THE FOLLOWING:
1. This is only part of the 2nd page that you need to know
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Bring Out Your MIPS Reference Cards!
Look for the following instructions:
nor addi beq move
Tell me everything you can about them, based on what you see on the Ref Card!
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Example 1
Syntax for add
add rd, rs, rt
destination, source1, source2
f = (g + h) (i + j)
i.e. $s0 = ($s1 + $s2) ($s3 + $s4)
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
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Example 2
f=g*h-i
i.e. $s0 = ($s1 * $s2) $s3
mult $s1, $s2
mflo $t0
# mflo directs where the answer of the mult should go
sub $s0, $t0, $s3
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Recap: The mult instruction
To multiply 2 integers together: li $t0, 5
li $t1, 6
mult $t1, $t0
mflo $t2
# t0 = 5
# t1 = 6
# multiply t0 * t1 # t2 = t0 * t1
mult cannot be used with an immediate value
Then we multiply our multiplier ($t0) with our multiplicand ($t1)
And we put the result in the destination reg ($t2) using the mflo instruction
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Memory Operations
Main memory used for composite data
e.g.: Arrays, structures, dynamic data
In MIPS, use the .data declaration to initialize memory values (must be above .text declaration)
Example: .data
var1: .word 42
.text
la $t0, var1
lw $t1, 0($t0)
# t0 = &var1
# t1 = *(&var1) = 42
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.data
name: .asciiz Lisa speaks rtn: .asciiz languages!
age: .word 7
Example
What does this do?
.text
main:
syscall
la $t2, age
lw $a0, 0($t2)
li $v0, 1
syscall
li $v0, 4
la $a0, rtn
syscall
li $v0, 10
syscall
li $v0, 4
la $a0, name
# la = load memory address
What goes in here?a
What goes in here?a
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.data Declaration Types
w/ Examples
var1: var2: var3: num1: num2: str1: str3: str2:
.byte 9
.half 63
.word 9433
.float 3.14
.double 6.28
.ascii Text
.asciiz Text # declare .space 5 # reserve
# declare # declare # declare # declare # declare # declare
a single byte with value 9
a 16-bit half-word w/ val. 63 a 32-bit word w/ val. 9433 32-bit floating point number 64-bit floating pointer number a string of chars
a null-terminated string
5 bytes of space (useful for arrays)
These are now reserved in memory and we can call them up by loading their memory address into the appropriate registers.
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YOUR TO-DOs for the Week
Do your reading for next class (see syllabus)
Work on Assignment #1 for lab (lab01)
Meet up in the lab this Friday
Do the lab assignment
You have to submit it as a PDF using Gradescope Due on Wednesday, 1/15, by 11:59:59 PM
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