[SOLVED] The Chinese University of Hong Kong Department of Electronic Engineering

The Chinese University of Hong Kong Department of Electronic Engineering
ELEG3202 Homework 3 Opamp Design Name: LEUNG Ka Nang Alex
StudentIDno.: 1009876531
1. Circuit
V+
I
1
V
2. Netlist
* Current-mirror amplifier .include ./mosfet_model.txt
Report
Co
M4 3 M3
M5 4 M6
vin- M1
M2 vin+ M9
2
M10
5
M7
M8
.subckt opamp vdd
vss vi+ 2
2
vdd vdd vdd vdd vss vss vss vss
vi- vo cmosn
cmosn cmosp cmosp cmosp cmosp cmosn cmosn cmosn cmosn
m1 3 m2 4 m3 3 m4 4 m5 5 m6 vo m7 5 m8 vo m9 2 m10 1 ib vdd .ends
vi- 2 vi+ 2
3 vdd 4 vdd 3 vdd 4 vdd 5 vss 5 vss 1 vss 1 vss 1 10u
w=20u l=2u
w=20u l=2u
w=60u l=2u
w=60u l=2u
w=60u l=2u
w=60u l=2u m=10 w=20u l=2u
w=20u l=2u m=10 w=20u l=2u m=2 w=20u l=2u
* Postive and negative supplies Written By: Prof. LEUNG Ka Nang Alex
p. 1
M 1 : M 2 = 1 : 1 M 3 : M 4 = 1 : 1 M 5 : M 6 = 1 : K M 7 : M 8 = 1 : K M9 : M10 = 2 : 1

vddvdd0 2.5 vss vss 0 -2.5
* Equivalent capacitive load cl vo 0 100p
* Step 1: Operation point and AC response
* Call sub-circuit opamp
x1 vdd vss 0 vi- vo opamp
* Added L, C and Vs for loop-gain analysis lx vo vi- 1t
cx 100 0 1t
vs vi- 100 dc=0 ac=1
.op
.ac dec 100 1 10meg
.probe v(vo)
.meas ac pm find v(vo) when mag(v(vo))=1
* Step 2: Output swing
*x1 vdd *vin vin *.dc vin *.probe
vss vin 0 vo opamp 0 dc=0
-20m 20m 1u
(vo)
* Step 3: Transient response as voltage buffer *x1 vdd vss vin vo vo opamp
*vin vin 0 *.trans 0.1n 4u *.probe v(vo) v(vin)
.end
pwl 0,0 1u,0 1.01u,1 3u,1 3.01u,0
3. Hand calculation
Given that nCox = 910-5A/V2, pCox = 310-5A/V2, VTHN = 1V, VTHP = -1V, n = 0.02V-1 and p = 0.02V-1.
Parameters:
I =10A, K =10, gm1 = 2(10e6)(9e5)(20/2)=1.34e4A/V2
r = 1 =500k,r = 1 =500k o6 (0.02)(10)(10e 6) o8 (0.02)(10)(10e 6)
VSD6(sat) = 2(10)(10e6) =0.149V, VDS8(sat) = (3e 5)(10)(60/2)
2(10)(10e6) =0.149V (9e 5)(10)(20/2)
Written By: Prof. LEUNG Ka Nang Alex
p. 2

Voltage gain: vo = Kgm1 (ro6 // ro8 )= (10)(1.34e 4)(500e 3//500e 3)= 335V/V d
Unity-gain bandwidth: UGF = Kgm1 = (10)(134e 6) = 2.13MHz Co (100e 12)(2 )
Slew rate: SR = KI = (10)(20e 6) = 2V/us Co 100e 12
Output swing: -2.5V + 0.149V (= -2.351V) Vo 2.5V 0.149V (= 2.351V) Phase Margin: PM of single-stage amplifier = 90o.
Supply current: IDD = (4 +10)(10e 6)=140A
Power consumption: P = (VDD VSS )I DD = [2.5 ( 2.5)]140e 6 = 700W 4. Simulation result
Simulation (refer to Lecture Notes 4)
Hand calculation
Voltage gain
324.70V/V
335V/V
UGF
2.29MHz
2.13MHz
SR
2.07V/s
2V/s
Output swing
-2.348V Vo 2.352V
-2.351V Vo 2.351V
Phase margin
89.46o
90o
Power consumption
720W
700W
Written By: Prof. LEUNG Ka Nang Alex
p. 3

5. Simulation plots
Voltage gain and UGF
Written By: Prof. LEUNG Ka Nang Alex p. 4

Output swing
Written By: Prof. LEUNG Ka Nang Alex p. 5

Slew rate
Power consumption
Written By: Prof. LEUNG Ka Nang Alex p. 6